CY2077_08 Datasheet, PDF (5/14 Pages) Cypress Semiconductor – High-accuracy EPROM Programmable Single-PLL Clock Generator

CY2077
Output Clock Switching Characteristics Commercial
Over the Operating Range^[4]
Parameter
Description
Test Conditions
t_1w
Output duty cycle at 1.4V, 1 – 40 MHz, C_L <= 50 pF
V_DD = 4.5 – 5.5V
40 – 125 MHz, C_L <= 25 pF
t_1w = t_1A ÷ t_1B
125 – 133 MHz, C_L <= 15 pF
t_1x
Output duty cycle at V_DD/2, 1 – 40 MHz, C_L <= 50 pF
V_DD = 4.5 – 5.5V
40 – 125 MHz, C_L <= 25 pF
t_1x = t_1A ÷ t_1B
125 – 133 MHz, C_L <= 15 pF
t_1y
Output duty cycle at V_DD/2, 1 – 40 MHz, C_L <= 30 pF
V_DD = 3.0 – 3.6V
40 – 100 MHz, C_L <= 15 pF
t_1y = t_1A ÷ t_1B
t₂
Output clock rise time
Between 0.8 – 2.0V, V_DD = 4.5V – 5.5V, C_L = 50 pF
Between 0.8 – 2.0V, V_DD = 4.5V – 5.5V, C_L = 25 pF
Between 0.8 – 2.0V, V_DD = 4.5V – 5.5V, C_L = 15 pF
Between 0.2V_DD – 0.8V_DD, V_DD= 4.5V – 5.5V, C_L = 50 pF
Between 0.2V_DD – 0.8V_DD, V_DD= 3.0V – 3.6V, C_L = 30 pF
Between 0.2V_DD – 0.8V_DD, V_DD= 3.0V – 3.6V, C_L = 15 pF
t₃
Output clock fall time
Between 0.8V –2.0V, V_DD = 4.5V – 5.5V, C_L = 50 pF
Between 0.8 – 2.0V, V_DD = 4.5V – 5.5V, C_L = 25 pF
Between 0.8 – 2.0V, V_DD = 4.5V – 5.5V, C_L = 15 pF
Between 0.2V_DD – 0.8V_DD, V_DD= 4.5V – 5.5V, C_L = 50 pF
Between 0.2V_DD – 0.8V_DD, V_DD= 3.0V – 3.6V, C_L = 30 pF
Between 0.2V_DD – 0.8V_DD, V_DD= 3.0V – 3.6V, C_L = 15 pF
t₄
Start-up time out of power PWR_DWN pin LOW to HIGH^[5]
down
t_5a
Power down delay time PWR_DWN pin LOW to output LOW
(synchronous setting)
(T= period of output CLK)
t_5b
Power down delay time PWR_DWN pin LOW to output LOW
(asynchronous setting)
t₆
Power up time
From power on^[5]
t_7a
Output disable time
OE pin LOW to output high-Z
(synchronous setting)
(T= period of output CLK)
t_7b
Output disable time
OE pin LOW to output high-Z
(asynchronous setting)
t₈
Output enable time
OE pin LOW to HIGH
(always synchronous
(T= period of output CLK)
enable)
t₉
Peak-to-peak period
V_DD = 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz, V_CO > 100 MHz
jitter
V_DD = 3.0V – 5.5V, Fo < 33 MHz
Min Typ Max Unit
45
55 %
45
55 %
45
55 %
45
55 %
45
55 %
45
55 %
45
55 %
40
60 %
1.8 ns
1.2 ns
0.9 ns
3.4 ns
4.0 ns
2.4 ns
1.8 ns
1.2 ns
0.9 ns
3.4 ns
4.0 ns
2.4 ns
1 2 ms
T/2 T + ns
10
10 15 ns
1 2 ms
T/2 T + ns
10
10 15 ns
T 1.5T ns
+
25ns
80 150 ps
0.3% 1% % of
F_O
Notes
4. Not all parameters measured in production testing.
5. Oscillator start time can not be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70Ω.
Document Number: 38-07210 Rev. *C
Page 5 of 14
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