CY2037 Datasheet, PDF (5/7 Pages) Cypress Semiconductor – High Accuracy EPROM Programmable PLL Die for Crystal Oscillators

PRELIMINARY
CY2037
Output Clock Switching Characteristics Over the Operating Range
Symbol
Description
Test Conditions
Min Typ
Max
t_1w
Output Duty Cycle at 1–27 MHz, C_L <= 50 pF
1.4V, V_DD = 4.5–5.5V 27–80 MHz, C_L <= 15pF
t_1w = t_1A ÷ t_1B
27–125 MHz, C_L <= 25pF
125–200 MHz, C_L <= 15pF
45
55
45
55
40
60
40
60
t_1x
Output Duty Cycle at 1–66.6 MHz, C_L <= 50 pF
V_DD/2, V_DD = 4.5–5.5V 66.6–125 MHz, C_L <= 25 pF
t_1x = t_1A ÷ t_1B
125–200 MHz, C_L <= 15pF
45
55
40
60
40
60
t_1y
Output Duty Cycle at 1–50 MHz, C_L <= 30 pF
V_DD/2, V_DD = 3.0–3.6 50–100 MHz, C_L <= 15pF
t_1y = t_1A ÷ t_1B
45
55
40
60
t_1z
Output Duty Cycle at 1–40 MHz, C_L <= 15 pF
V_DD/2, V_DD = 2.7–3.6V 40–66.6 MHz, C_L <= 15 pF
t_1z = t_1A ÷ t_1B
45
55
40
60
t₂
Output Clock Rise time Between 0.8 –2.0V, V_DD = 4.5V–5.5V, C_L = 50 pF
1.8
Between 0.8 –2.0V, V_DD = 4.5V–5.5V, C_L = 25 pF
1.2
Between 0.8 –2.0V, V_DD = 4.5V–5.5V, C_L = 15 pF
0.9
Between 0.2V_DD– 0.8V_DD, V_DD= 4.5V–5.5V, C_L = 50 pF
3.4
Between 0.2V_DD– 0.8V_DD, V_DD= 3.0V–3.6V, C_L = 30 pF
4.0
Between 0.2V_DD– 0.8V_DD, V_DD= 3.0V–3.6V, C_L = 15 pF
2.4
Between 0.2V_DD– 0.8V_DD, V_DD= 2.7V–3.6V, C_L = 15 pF
4.0
t₃
Output Clock Fall time Between 0.8V–2.0V, V_DD = 4.5V–5.5V, C_L = 50 pF
Between 0.8 –2.0V, V_DD = 4.5V–5.5V, C_L = 25 pF
Between 0.8 –2.0V, V_DD = 4.5V–5.5V, C_L = 15 pF
Between 0.2V_DD– 0.8V_DD, V_DD= 4.5V-5.5V, C_L = 50 pF
Between 0.2V_DD– 0.8V_DD, V_DD= 3.0V–3.6V, C_L = 30 pF
Between 0.2V_DD– 0.8V_DD, V_DD= 3.0V–3.6V, C_L = 15 pF
Between 0.2V_DD– 0.8V_DD, V_DD= 2.7V–3.6V, C_L = 15 pF
t₄
Start-up time out of
PWR_DWN or OE pin LOW to HIGH^[2]
power-down
1.8
1.2
0.9
3.4
4.0
2.4
4.0
1
2
t_5a
Power Down delay time PWR_DWN pin HIGH to output LOW
(synchronous setting) (T=frequency oscillator period)
T/2
T+10
t_5b
Power Down delay time PWR_DWN pin HIGH to output LOW
(asynchronous setting)
t₆
Power Up time
From power on^[2]
t_7a
Output disable time
OE pin HIGH to output Hi-Z
(synchronous setting) (T=frequency oscillator period)
10
15
1
2
T/2
T+10
t_7b
Output disable time
OE pin HIGH to output Hi-Z
(asynchronous setting)
10
15
t₈
Output enable time
PWR_DWN or OE pin LOW to HIGH
100
t₉
Peak-to-Peak Period V_DD= 4.5V–5.5V, Fo > 33 MHz, VCO > 100 MHz
Jitter
V_DD= 3.0V–3.6V, Fo > 33 MHz, VCO >100 MHz
V_DD= 3.0V–5.5V, Fo <33 MHz
±50
±75
±100
±100
±125
±250
Note:
2. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
Unit
%
%
%
%
%
%
%
%
%
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ms
ns
ns
ns
ps
ps
ps
5