CY14C256I Datasheet, PDF (5/41 Pages) Cypress Semiconductor – 256-Kbit (32 K x 8) Serial (I2C) nvSRAM with Real Time Clock Full-featured RTC

CY14C256I
CY14B256I, CY14E256I
Data Validity
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH: START and STOP condition. The
START and STOP conditions are generated by the master to
signal the beginning and end of a communication sequence on
the I²C bus.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I²C begins
with the master generating a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
If a Repeated START condition is generated instead of a STOP
condition, the bus continues to be busy. The ongoing transaction
on the I²C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SDA
SCL
handbook, full pagewidth
SDA
SCL
S
P
START Condition
STOP Condition
Figure 4. Data Transfer on the I²C Bus
P
MSB
Acknowledgement
signal from slave
Acknowledgement ^Sr
signal from receiver
SCL
S
or
Sr
1
2
START or
Repeated START
condition
7
8
9
ACK
Byte complete,
interrupt within slave
1
2
3-8
9
ACK
Clock line held LOW while
interrupts are serviced
Sr
or
P
STOP or
Repeated START
condition
Byte Format
Each operation in I²C is done using 8-bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
Acknowledge / No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I²C bus needs a response with an ACK signal
by the receiver to continue the operation. Failing to do so is
considered as a NACK state. NACK is the state where receiver
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
■ The master did not receive valid data due to noise.
■ The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE
operation in these cases:
■ nvSRAM did not receive valid data due to noise.
■ The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Document #: 001-65230 Rev. *B
Page 5 of 41
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