CY14C101I Datasheet, PDF (5/42 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) Serial (I2C) nvSRAM with Real Time Clock

PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Figure 2. System Configuration using Serial (I²C) nvSRAM
Microcontroller
Vcc
SDA
R_Pmin = (V_CC - V_OLmax) / I_OL
R_Pmax = t_r / C_b
SCL
A1
SCL
A2
SDA
WP
Vcc
A1
SCL
A2
SDA
WP
Vcc
A1
SCL
A2
SDA
WP
CY14X101I
CY14X101I
CY14X101I
Data Validity
#0
#1
#3
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH: START and STOP condition. The
START and STOP conditions are generated by the master to
signal the beginning and end of a communication sequence on
the I²C bus.
START Condition (S)
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I²C begins
with the master generating a START condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
If a Repeated START condition is generated instead of a STOP
condition, the bus continues to be busy. The ongoing transaction
on the I²C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
Figure 3. START and STOP Conditions
full pagewidth
SDA
SCL
S
START Condition
SDA
SCL
P
STOP Condition
Document #: 001-54391 Rev. *C
Page 5 of 42
[+] Feedback