CY7C68013A-128AXC Datasheet, PDF (49/66 Pages) Cypress Semiconductor – EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller

CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.13 Slave FIFO Output Enable
Figure 9-14. Slave FIFO Output Enable Timing Diagram^[20]
SLOE
DATA
t_OEon
t_OEoff
Table 28. Slave FIFO Output Enable Parameters
Parameter
t_OEon
t_OEoff
Description
SLOE assert to FIFO DATA output
SLOE deassert to FIFO DATA hold
Min
Max
Unit
10.5
ns
10.5
ns
9.14 Slave FIFO Address to Flags/Data
Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram^[20]
FIFOADR [1.0]
FLAGS
DATA
t_XFLG
t_XFD
N
N+1
Table 29. Slave FIFO Address to Flags/Data Parameters
Parameter
Description
Min
Max
Unit
t_XFLG
t_XFD
FIFOADR[1:0] to FLAGS output propagation delay
–
10.7
ns
FIFOADR[1:0] to FIFODATA output propagation delay
–
14.3
ns
9.15 Slave FIFO Synchronous Address
Figure 9-16. Slave FIFO Synchronous Address Timing Diagram^[20]
IFCLK
SLCS/FIFOADR [1:0]
Table 30. Slave FIFO Synchronous Address Parameters ^[21]
Parameter
t_IFCLK
t_SFA
t_FAH
Description
Interface clock period
FIFOADR[1:0] to clock setup time
Clock to FIFOADR[1:0] hold time
t_SFA t_FAH
Min
20.83
25
10
Max
200
–
–
Unit
ns
ns
ns
Document #: 38-08032 Rev. *V
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