S6J311A Datasheet, PDF (47/92 Pages) Cypress Semiconductor – 32-Bit Traveo™ Family S6J3110 Series Microcontroller Datasheet

S6J311A, S6J3119, S6J3118
Relationship between the oscillation clock frequency and internal clock frequency
Oscillation Clock
Frequency
4 MHz
4 MHz
Main Clock
4 MHz
4 MHz
PLL Multiplier
Setting
144
120
PLL Output
Division Setting
6
6
− Oscillation circuit example
PLL Clock
96 MHz
80 MHz
X0
X1
R
C1
C2
Notes:
· When configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator
manufacturers for the design.
· The maximum PLL clock frequency must be 96MHz.
Output division configuration can be set by the following.
- PLLDIVM bit in SYSC0_RUNPLL0CNTR register
- PLLDIVM bit in SYSC0_PSSPLL0CNTR register
- SSCGDIVM bit in SYSC0_RUNSSCG0CNTR0 register
- SSCGDIVM bit in SYSC0_PSSSSCG0CNTR0 register
(e.g. If PLLout is 576MHz, these settings must be configured as "multiply by 6" and over multiplication
setting)
AC characteristics are specified by the following measurement reference voltage values.
− Input signal waveform
− Output signal waveform
Hysteresis input pin (Automotive)
0.8VCC
0.5VCC
Output pin
2.4V
0.8V
Hysteresis input pin (CMOS Schmitt)
0.7VCC
0.3VCC
Hysteresis input pin (TTL)
2.3V
0.8V
Document Number: 002-04632 Rev.*B
Page 47 of 92