CY8C34_11 Datasheet, PDF (47/126 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C34 Family
Data Sheet
option to be double synchronized. The synchronization clock is
the system clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
4 IO Control Signal Connections from
UDB Array Digital System Interface
DO
DI
Figure 7-16. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
7.5 CAN
DO
DO
DO
DO
DO
DO
DO
DO
PIN 0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7
Port i
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The CAN peripheral is a fully functional Controller Area Network
(CAN) supporting communication baud rates up to 1 Mbps. The
CAN controller implements the CAN2.0A and CAN2.0B
specifications as defined in the Bosch specification and
conforms to the ISO-11898-1 standard. The CAN protocol was
originally designed for automotive applications with a focus on a
high level of fault detection. This ensures high communication
reliability at a low cost. Because of its success in automotive
applications, CAN is used as a standard communication protocol
for motion oriented machine control networks (CANOpen) and
factory automation applications (DeviceNet). The CAN controller
features allow the efficient implementation of higher level
protocols without affecting the performance of the
microcontroller CPU. Full configuration support is provided in
PSoC Creator.
Figure 7-18. CAN Bus System Implementation
CAN Node 1
PSoC
CAN
Drivers
CAN Node 2
CAN Node n
CAN Controller
En
Tx Rx
CAN Transceiver
CAN_H CAN_L
CAN_H CAN_L
CAN Bus
CAN_H CAN_L
Document Number: 001-53304 Rev. *K
Page 47 of 126
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