CYRF69213 Datasheet, PDF (44/85 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69213
Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the CYRF69213 devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually. The registers also
provide a mechanism by which a user may clear all pending
and posted interrupts, or clear individual posted or pending
interrupts.
The following table lists all interrupts and the priorities that are
available in the CYRF69213.
Table 65.Interrupt Numbers, Priorities, Vectors
Interrupt Interrupt
Priority Address
0
0000h Reset
Name
1
0004h POR/LVD
2
0008h INT0
3
000Ch SPI Transmitter Empty
4
0010h SPI Receiver Full
5
0014h GPIO Port 0
6
0018h GPIO Port 1
7
001Ch INT1
8
0020h EP0
9
0024h EP1
10
0028h EP2
11
002Ch USB Reset
12
0030h USB Active
13
0034h 1-ms Interval timer
14
0038h Programmable Interval Timer
15
003Ch Reserved
16
0040h Reserved
Table 65.Interrupt Numbers, Priorities, Vectors (continued)
Interrupt Interrupt
Priority Address
Name
17
0044h 16-bit Free Running Timer Wrap
18
0048h INT2
19
004Ch Reserved
20
0050h GPIO Port 2
21
0054h Reserved
22
0058h Reserved
23
005Ch Reserved
24
0060h Reserved
25
0064h Sleep Timer
Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in Figure 19 clocking in a ‘1’. The
interrupt will remain posted until the interrupt is taken or until
it is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register).
All pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which will be taken by
the M8C if the Global Interrupt Enable bit is set in the CPU_F
register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor
does it prevent an interrupt from being posted. It simply
prevents a posted interrupt from becoming pending.
Nested interrupts can be accomplished by re-enabling inter-
rupts inside an interrupt service routine. To do this, set the IE
bit in the Flag Register.
A block diagram of the CYRF69213 Interrupt Controller is
shown in Figure 19.
Figure 19. Interrupt Controller Block Diagram
InterruptTaken
or
INT_CLRxWrite
Posted
Interrupt
Pending
Interrupt
Priority
Encoder
Interrupt
Source
(Timer,
GPIO,etc.)
R
1
DQ
Document #: 001-07552 Rev. *B
INT_MSKx
Mask Bit Setting
Interrupt Vector
CPU_F[0]
GIE
Interrupt
Request
M8C Core
Page 44 of 85
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