CY7C601XX_08 Datasheet, PDF (44/67 Pages) Cypress Semiconductor – enCoRe™ II Low Voltage Microcontroller

CY7C601xx, CY7C602xx
17. Serial Peripheral Interface (SPI)
The SPI Master and Slave Interface core logic runs on the SPI clock domain. The SPI clock is a divider off of the CPUCLK when in
Master Mode. SPI is a four pin serial interface comprised of a clock, an enable, and two data pins.
Figure 17-1. SPI Block Diagram
Register Block
SCK Speed Sel
SCK Clock Generation
Master/Slave Sel
SCK Clock Select
SCK_OE
SCK Polarity
SCK Phase
Little Endian Sel ^LE_SEL
SCK Clock Phase/Polarity
Select
SCK
SPI State Machine
SS_N
Data (8 bit)
Load
Empty
SCK
LE_SEL
Output Shift Buffer
Master/Slave Set
Shift Buffer
GPIO Block
SS_N
SS_N_OE
MISO_OE
MISO/MOSI
Crossbar
MOSI_OE
SCK
SS_N
MISO
Data (8 bit)
Load
Full
Input Shift Buffer
MOSI
Sclk Output Enable
Slave Select Output Enable
Master IN, Slave Out OE
Master Out, Slave In, OE
SCK_OE
SS_N_OE
MISO_OE
MOSI_OE
Document 38-16016 Rev. *D
Page 44 of 67
[+] Feedback