MB91460Q Datasheet, PDF (40/153 Pages) Cypress Semiconductor – 32-bit RISC, load/store architecture, five-stage pipeline

MB91460Q Series
9.4.3 CCR (Condition Code Register)
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SV S I N Z V C
Initial value
- 000XXXXB
SV : Supervisor flag
S : Stack flag
I : Interrupt enable flag
N : Negative enable flag
Z : Zero flag
V : Overflow flag
C : Carry flag
9.4.4 SCR (System Condition Register)
bit 10 bit 9 bit 8
D1 D0 T
Initial value
XX0B
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution of user programs.
9.4.5 ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
ILM4 ILM3 ILM2 ILM1 ILM0
Initial value
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111_B” at reset.
9.4.6 PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
Document Number: 002-04617 Rev. *A
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