Z9975 Datasheet, PDF (4/8 Pages) Cypress Semiconductor – 3.3V, 150MHz, Multi-Output Zero Delay Buffer

Z9975
3.3V, 150MHz, Multi-Output Zero Delay Buffer
Pin Description (Cont.)
PIN No. Pin Name I/O
11
VCO_Sel1
I
40,38,36,
Qb(0:4)
O
34,32
50,48,46,
Qc(0:3)
O
44
52
VCO_Sel0
I
27,42
n/c
-
12
VDDI
P
15
VSSI
P
13,
VDDA
P
17,22,26
VDDa
P
19,24
VSSa
P
28, 30 VDDFB / VSSFB P
33,37,41
VDDb
P
35,39
VSSb
P
45,49
VDDc
P
43,47,51
VSSc
P
1
VSSA
P
Description
Output Division Selection contains an internal pulldown resistor. When left floating or pulled
to VSS (Logic 0) output frequencies are described by Output Frequency Table 2, when
driven to VDD (Logic 1), output frequencies are described by Table 3.
High drive, Low Voltage CMOS, Output clock buffers, Bank Qb. Their divide ratio is
programmed by fselb, pin#4.
High drive, Low Voltage CMOS, Output clock buffers, Bank Qc. Their divide ratio is
programmed by fselc, pin#5.
Input select pin for setting the divider of the VCO output. It has a 250KΩ internal pull-down.
If VCO_sel = 0, then the PLL VCO output is divided by 2. If VCO_sel = 1, then the PLL
VCO output is divided by 4. See fig.1, page2; table 1, page1, table 2, page 3.
These pins are not connected internally. They may be attached to a ground plane.
Power for input logic circuitry.
Ground for input logic circuitry.
Power and Ground supply pins for internal Analog circuitry.
3.3V supply for Qa(0:4) output bank, and fselFB1 input.
Common ground for Qa(0:4) output bank, and fselFB1 input.
Power and ground supply pins for QFB output and FB_In input pins and digital circuitry.
3.3V supply for Qb(0:4) output bank.
Common ground for Qb(0:4) output bank.
3.3V supply for Qc(0:3) output bank and VCO_sel pin.
Common ground for Qc(0:3) output bank and VCO_sel pin.
Analog Ground
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass
capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of
the traces.
Glitch-Free Output Frequency Transitions
Customarily when zero delay buffers have their internal counter’s changed “on the fly’ their output clock periods will:
A. Contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either
the old or new frequency that is being transitioned to.
B. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old
or new frequency that is being transitioned to.
This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly” while it is operating: Fsela, Fselb, Fselc, VCO_Sel, FselFB1,
and FselFB2.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07091 Rev. *B
12/26/2002
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