W152_02 Datasheet, PDF (4/8 Pages) Cypress Semiconductor – Spread Aware™, Eight Output Zero Delay Buffer

W152
Absolute Maximum Ratings^[3]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
.
Parameter
Description
V_DD, V_IN
T_STG
T_A
T_B
P_D
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Power Dissipation
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Rating
Unit
–0.5 to +7.0
V
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
0.5
W
DC Electrical Characteristics: T_A =0°C to 70°C, V_DD = 3.3V ±10%
Parameter
Description
Test Condition
I_DD
Supply Current
Unloaded, 100 MHz
V_IL
Input Low Voltage
V_IH
Input High Voltage
V_OL
Output Low Voltage
I_OL = 12 mA (-11, -12)
I_OL = 8 mA (-1, -2, -3, -4)
V_OH
Output High Voltage
I_OH = 12 mA (-11, -12)
I_OH = 8 mA (-1, -2, -3, -4)
I_IL
Input Low Current
V_IN = 0V
I_IH
Input High Current
V_IN = V_DD
Min.
Typ.
Max.
Unit
40
mA
0.8
V
2.0
V
0.4
V
2.4
V
50
µA
50
µA
AC Electrical Characteristics: T_A = 0°C to +70°C, V_DD = 3.3V ±10%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
f_IN
f_OUT
Input Frequency
Output Frequency
Note 4
15-pF load^[9]
15
140
MHz
15
140
MHz
t_R
Output Rise Time (-1, -2, -3, -4) 0.8V to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-11, -12)
0.8V to 0.8V, 15-pF load
1.5
ns
t_F
Output Fall Time (-1, -2, -3, -4) 2.0V to 0.8V, 15-pF load
2
2.5
ns
Output Rise Time (-11, -12)
2.0V to 0.8V, 20-pF load
1.5
ns
t_ICLKR
t_ICLKF
t_PD
t_SK
t_D
Input Clock Rise Time^[5]
Input Clock Fall Time^[5]
FBIN to REF Skew^{[6, 7]}
Output to Output Skew
Duty Cycle
All outputs loaded equally^[11]
15-pF load^{[8, 9]}
45
4.5
ns
4.5
ns
350
ps
215
ps
50
55
%
t_LOCK
PLL Lock Time
Power supply stable
1.0
ms
t_JC
Jitter, Cycle-to-Cycle
Note 10
225
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). See
Table 1.
5. Longer input rise and fall time will degrade skew and jitter performance.
6. All AC specifications are measured with a 50Ω transmission line.
7. Skew is measured at V_DD/2 on rising edges.
8. Duty cycle is measured at V_DD/2.
9. For the higher drive -11 and -12, the load is 20 pF.
10. For frequencies above 25 MHz CY - CY = 125 ps.
11. Measured across all outputs. Maximum skew between outputs in the same bank is 100 ps.
Document #: 38-07148 Rev. *A
Page 4 of 8