STK15C88_11 Datasheet, PDF (4/17 Pages) Cypress Semiconductor – 256-Kbit (32 K x 8) PowerStore nvSRAM Unlimited RECALL Cycles

STK15C88
Device Operation
Software STORE
The STK15C88 is a versatile memory chip that provides several Data is transferred from the SRAM to the nonvolatile memory by
modes of operation. The STK15C88 can operate as a standard a software address sequence. The STK15C88 software STORE
32 K × 8 SRAM. It has a 32 K × 8 nonvolatile element shadow to cycle is initiated by executing sequential CE controlled READ
which the SRAM information can be copied, or from which the cycles from six specific address locations in exact order. During
SRAM can be updated in nonvolatile mode.
the STORE cycle, an erase of the previous nonvolatile data is
SRAM Read
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
The STK15C88 performs a READ cycle whenever CE and OE
ly. ^{are LOW while WE is HIGH. The address specified on pins A0–14}
determines the 32,768 data bytes accessed. When the READ is
n _{initiated by an address transition, the outputs are valid after a}
o _{delay of tAA (READ cycle 1). If the READ is initiated by CE or OE,}
s _{the outputs are valid at tACE or at tDOE, whichever is later (READ}
m _{cycle 2). The data outputs repeatedly respond to address}
ra ^{changes within the t}AA ^{access time without the need for transi-}
g tions on any control input pins, and remains valid until another
o address change or until CE or OE is brought HIGH.
pr _{SRAM Write}
tion ^{A WRITE cycle is performed whenever CE and WE are LOW.}
c ^{The address inputs must be stable prior to entering the WRITE}
. _{u cycle and must remain stable until either CE or WE goes HIGH}
s _{d at the end of the cycle. The data on the common I/O pins DQ0–7}
ign ^{ro are written into the memory if it has valid tSD, before the end of}
s ^{p a WE controlled WRITE or before the end of an CE controlled}
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
e g _{data bus contention on common I/O lines. If OE is left LOW,}
d _{in internal circuitry turns off the output buffers tHZWE after WE goes}
w ^o _LOW.
r ^{ne ong AutoStore Operation}
fo ^rt _{The STK15C88 uses the intrinsic system capacitance to perform}
d ^{o an automatic STORE on power down. As long as the system}
e _pp power supply takes at least t_STORE to decay from V_SWITCH down
d _u to 3.6 V, the STK15C88 will safely and automatically store the
n s _{SRAM data in nonvolatile elements on power down.}
me ^{to In order to prevent unneeded STORE operations, automatic}
STOREs will be ignored unless at least one WRITE operation
m ⁿ _{has taken place since the most recent STORE or RECALL cycle.}
co ^{tio Software initiated STORE cycles are performed regardless of}
e ^{c whether a WRITE operation has taken place.}
ot ^{r odu Hardware RECALL (Power Up)}
N _{pr During power up or after any low power condition (VCC <}
In ^{VRESET), an internal RECALL request is latched. When VCC}
once again exceeds the sense voltage of V_SWITCH, a RECALL
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. After the
t_STORE cycle time is fulfilled, the SRAM is again activated for
READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t_RECALL cycle time, the SRAM is once
cycle is automatically initiated and takes t_HRECALL to complete. ^{again ready for READ and WRITE operations. The RECALL}
If the STK15C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
situation, a 10 Kohm resistor is connected either between WE
and system V_CC or between CE and system V_CC.
Document Number: 001-50593 Rev. *C
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