CYWB0224ABS Datasheet, PDF (4/6 Pages) Cypress Semiconductor – West BridgeTM AstoriaTM

ADVANCE INFORMATION
CYWB0224ABS/CYWB0224ABM
Table 1. Astoria Pin Assignments (continued)
Non-multiplexing Multiplexing
Pin Name
SRAM
SDIO and NAND NAND only
Dual SDIO
Configuration Configuration Configuration
SD_D[7:0]
SD_CLK
NAND_IO[15:8] SD_D[7:0]
/ PD[7:0] (GPIO)
NAND_CE8#/N SD_CLK
AND_R/B4#
SD_CMD
NAND_CE7#/N SD_CMD
AND_R/B3#
SD_POW
NAND_CE6# SD_POW
SD_WP
NAND_CE5# SD_WP
NAND_IO[7:0]
NAND_IO[7:0]
NAND_CLE
NAND_CLE
NAND_ALE
NAND_ALE
NAND_CE#
NAND_CE#
NAND_RE#
NAND_RE#
NAND_WE#
NAND_WE#
NAND_WP#
NAND_WP#
NAND_R/B#
NAND_R/B#
NAND_CE2#
NAND_CE2#
RESETOUT /
NAND_R/B2#
NAND_R/B2#
GPIO[0] / SD_CD / NAND_CE4#
NAND_CE4#
SD2_D[7:0]
SD2_CLK
SD2_CMD
SD2_POW
N/C
N/C
PA-5 (GPIO)
SD2_WP
RESETOUT
PC-4 (GPIO[0]) /
SD_CD
GPIO[1] /
NAND_CE3#
RESET#
WAKEUP
XTALIN
XTALOUT
XTALSLC[1:0]
NANDCFG
TEST[2:0]
PVDDQ
SNVDDQ
UVDDQ
SSVDDQ
GVDDQ
AVDDQ
XVDDQ
VDD
VDD33
UVSSQ
AVSSQ
VGND
NAND_CE3# PC-5 (GPIO[1]) /
SD2_CD
PNAND
IO
SPI
Pin Description
Power Domain
NAND and GPIO
Configuration
SDIO and
GPIO
Configuration
NAND_IO[15:8] / SD_D[7:0]
PD[7:0] (GPIO)
IO SD Data bus/NAND Upper IO bus
PC-7 (GPIO) /
NAND_CE8# /
NAND_R/B4#
SD_CLK
IO SD Clock/NAND CE8#/NAND R/B4#
PC-3 (GPIO) /
NAND_CE7# /
NAND_R/B3#
SD_CMD
IO SD Command, NAND CE7#, or
NAND_R/B3#
SSVDDQ
VGND
PC-6 (GPIO) /
NAND_CE6#
SD_POW
IO SD Power Control/NAND CE6#
PC-1 (GPIO) /
NAND_CE5#
NAND_IO[7:0]
NAND_CLE
NAND_ALE
NAND_CE#
NAND_RE#
NAND_WE#
SD_WP
IO GPIO (SD Write Protection Microswitch) or
NAND CE5#
PB[7:0] (GPIO) IO NAND Lower IO bus/2^nd SD Data Bus
PA-6 (GPIO)
IO CMD Latch Enable/2^nd SD Clock
PA-7 (GPIO)
IO Address Latch Enable/2^nd SD CMD
PC-0 (GPIO)
IO Chip Enable/2^nd SD Power Control
N/C
O Read Enable
N/C
O Write Enable
SNVDDQ
VGND
NAND_WP#
NAND_R/B#
PA-5 (GPIO)
IO Write Protect
I Ready/Busy/2^nd SD WP
NAND_CE2#
PC-2 (GPIO) IO Chip Enable 2
NAND_R/B2# / RESETOUT
RESETOUT
IO RESET OUT/NAND Busy/Ready
PC-4 (GPIO[0]) /
NAND_CE4#
PC-5 (GPIO[1]) /
NAND_CE3#
PC-4
(GPIO[0]) /
SD_CD
PC-5
(GPIO[1])
IO General Input/Output 0 or SD/MMC Card
Detection or NAND CE4#
IO General Input/Output 1 or NAND CE3#
GVDDQ
VGND
I RESET
I Wake Up Signal
I Crystal/Clock IN
O Crystal Out
XVDDQ
VGND
I Clock Select 0 and 1
I S Port Configuration
I Test Configuration
GVDDQ
VGND
PWR Processor interface VDD
PWR NAND VDD
PWR USB VDD
PWR SDIO VDD
PWR Miscellaneous IO VDD
PWR Analog VDD
PWR Crystal VDD
PWR Core VDD
PWR Independent 3.3V nominal
PWR USB GND
PWR Analog GND
PWR Core GND
Document #: 001-11710 Rev. *A
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