CYM1831 Datasheet, PDF (4/8 Pages) Cypress Semiconductor – 64K x 32 Static RAM Module

Switching Waveforms
Read Cycle No. 1 ^{[7, 8]}
t_RC
ADDRESS
DATA OUT
t_AA
t_OHA
PREVIOUS DATA VALID
CYM1831
DATA VALID
Read Cycle No . 2^{[7, 9]}
CS
t_RC
t_ACS
OE
DATA OUT
V_CC
SUPPLY
CURRENT
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCS
t_PU
50%
Notes:
7. WE is HIGH for read cycle.
8. Device is continuously selected, CS = V_IL and OE= V_IL.
9. Address valid prior to or coincident with CS transition LOW.
DATA VALID
t_HZOE
t_HZCS
HIGH
IMPEDANCE
t_PD
ICC
50%
ISB
Document #: 38-05270 Rev. **
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