CYD01S36V Datasheet, PDF (4/28 Pages) Cypress Semiconductor – FLEx36 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM

PRELIMINARY
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Pin Definitions
Left Port
A_0L–A_18L
Right Port
A_0R–A_18R
Address Inputs.
Description
BE_0L–BE_3L
BUSY_L[2,5]
BE_0R–BE_3R
BUSY_R[2,5]
Byte Enable Inputs. Asserting these signals enables Read and Write operations
to the corresponding bytes of the memory array.
Port Busy Output. When the collision is detected, a BUSY is asserted.
C_L
CE0_L[11]
CE1_L[10]
C_R
CE0_R[11]
CE1_R[10]
Input Clock Signal.
Active Low Chip Enable Input.
Active High Chip Enable Input.
DQ_0L–DQ_35L
DQ_0R–DQ_35R Data Bus Input/Output.
OE_L
INT_L
LowSPD_L[2,4]
PORTSTD[1:0]_L[2,4]
R/W_L
READY_L[2,5]
CNT/MSK_L[10]
ADS_L[11]
CNTEN_L[11]
CNTRST_L[10]
CNTINT_L[12]
WRP_L[2,3]
RET_L[2,3]
FTSEL_L[2,3]
VREF_L[2,4]
OE_R
Output Enable Input. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
INT_R
Mailbox Interrupt Flag Output. The mailbox permits communications between
ports. The upper two memory locations can be used for message passing. INT_L is
asserted LOW when the right port writes to the mailbox location of the left port, and
vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of
its mailbox.
LowSPD_R[2,4] ^{Port Low Speed Select Input.}
PORTSTD[1:0]_R[2,4] ^{Port Address/Control/Data I/O Standard Select Inputs.}
R/W_R
READY_R[2,5]
CNT/MSK_R[10]
Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from
the dual port memory array.
Port Ready Output. This signal will be asserted when a port is ready for normal
operation.
Port Counter/Mask Select Input. Counter control input.
ADS_R[11]
Port Counter Address Load Strobe Input. Counter control input.
CNTEN_R[11]
Port Counter Enable Input. Counter control input.
CNTRST_R[10] Port Counter Reset Input. Counter control input.
CNTINT_R[12]
WRP_R[2,3]
Port Counter Interrupt Output. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
Port Counter Wrap Input. The burst counter wrap control input.
RET_R[2,3]
Port Counter Retransmit Input. Counter control input.
FTSEL_R[2,3]
VREF_R[2,4]
Flow-Through Select. Use this pin to select Flow-Through mode. When is
de-asserted, the device is in pipelined mode.
Port External High-Speed IO Reference Input.
V_DDIOL
REV_L ^{[2, 3, 4]}
V_DDIOR
REV_R ^{[2, 3, 4]}
Port IO Power Supply.
Reserved pins for future features.
MRST
TRST^[2,5]
Master Reset Input. MRST is an asynchronous input signal and affects both ports.
A maser reset operation is required at power-up.
JTAG Reset Input.
TMS
TDI
JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
JTAG Test Data Input. Data on the TDI input will be shifted serially into selected
registers.
Document #: 38-06076 Rev. *B
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