CY7C68023_12 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – EZ-USB NX2LP™ USB 2.0 NAND Flash Controller

CY7C68023/CY7C68024
Additional Pin Descriptions
DPLUS, DMINUS
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB. General guidelines are given at the end of this document.
Figure 2. XTALIN, XTALOUT Diagram
12 pF
24-MHz Xtal
12-pF capacitor
values assume a
trace capacitance
of 3 pF per side on a
four-layer FR4 PCB
12 pF
XTALIN
XTALOUT
The NX2LP requires a 24 MHz (±100 ppm) signal to derive
internal timing. Typically, a 24 MHz (20 pF, 500 W,
parallel-resonant fundamental mode) crystal is used, but a
24 MHz square wave from another source can also be used. If a
crystal is used, connect its pins to XTALIN and XTALOUT, and
also through 12 pF capacitors to GND. If an alternate clock
source is used, apply it to XTALIN and leave XTALOUT open.
Data[7-0]
The Data[7-0] I/O pins provide an 8-bit interface to a NAND Flash
device. These pins are used to transfer address, command, and
read/write data between the NX2LP and NAND Flash.
R_B[2-1]#
The Ready/Busy input pins are used to determine the state of the
currently selected NAND Flash device. These pins must be
pulled HIGH through a 2k-4k resistor. These pins are pulled LOW
by the NAND Flash when it is busy.
WE#
The Write Enable output pin is used by the NAND Flash to latch
commands, address, and data during the rising edge of the
pulse.
RE[1-0]#
The Read Enable output pins are used to control the data flow
from the NAND Flash devices. The device presents valid data
and increments its internal column address counter by one step
on each falling edge of the Read Enable pulse. A 10k pull up is
an option For RE1-0#.
CLE
The Command Latch Enable output pin is used to indicate that
the data on the I/O bus is a command. The data is latched into
the NAND Flash control register on the rising edge of WE# when
CLE is HIGH.
ALE
The Address Latch Enable output pin is used to indicate that the
data on the I/O bus is an address. The data is latched into the
NAND Flash address register on the rising edge of WE# when
ALE is HIGH.
LED1#
The Data Activity LED output pin is used to indicate data transfer
activity. LED1# is asserted LOW at the beginning of a data
transfer, and set to a high Z state when the transfer is complete.
If this functionality is not utilized, leave LED1# floating.
LED2#
The Chip Active LED output pin is used to indicate proper device
operation. LED2# is asserted LOW when the NX2LP is powered
and initialized. It is placed in a high Z state under all other
conditions. If this functionality is not used, leave LED2# floating.
WP_SW#
The Write-protect Switch input pin is used to select whether or
not NAND Flash write-protection is enabled by the NX2LP. When
the pin is asserted LOW, the NAND Flash is write protected and
any attempts to write to the configuration data memory are
blocked.
CE[7-0]#
The Chip Enable output pins are used to select the NAND Flash
that the NX2LP interfaces. Unused Chip Enable pins should be
left floating.
RESET#
Asserting RESET# for 10 ms resets the NX2LP. A reset and/or
watchdog chip is recommended to ensure that startup and
brownout conditions are properly handled.
Document #: 38-08055 Rev. *G
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