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CY7C192 Datasheet, PDF (4/10 Pages) Cypress Semiconductor – 64K x 4 Static RAM with Separate I/O
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CY7C192
Switching Characteristics Over the Operating Range[6]
7C192-12
7C192-15
7C192-20
7C192-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
tAA
tOHA
Read Cycle Time
12
15
20
25
ns
Address to Data Valid
12
15
20
25
ns
Output Hold from
3
3
3
3
ns
Address Change
tACE
CE LOW to
Data Valid
12
15
20
25
ns
tLZCE
CE LOW to
Low Z[7]
3
3
3
3
ns
tHZCE
CE HIGH to
High Z[7,8]
5
7
9
11
ns
tPU
CE LOW to
Power-Up
0
0
0
0
ns
tPD
CE HIGH to
Power-Down
WRITE CYCLE[9]
12
15
20
25
ns
tWC
Write Cycle Time
12
15
20
25
ns
tSCE
CE LOW to
Write End
9
10
15
18
ns
tAW
Address Set-Up to
9
Write End
10
15
20
ns
tHA
Address Hold from
0
0
0
0
ns
Write End
tSA
Address Set-Up to
0
0
0
0
ns
Write Start
tPWE
WE Pulse Width
8
tSD
Data Set-Up to
8
Write End
9
15
18
ns
9
10
10
ns
tHD
Data Hold from
0
0
0
0
ns
Write End
tLZWE
WE HIGH to
Low Z (7C192)[7]
3
3
3
3
ns
tHZWE
WE LOW to
High Z (7C192)[7,8]
7
7
10
11
ns
tDWE
WE LOW to Data Valid
12
15
20
25
ns
(7C191)
tADV
Data Valid to
Output Valid (7C191)
12
15
20
20
ns
tDCE
CE LOW to Data Valid
12
15
20
25
ns
(7C191)
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 through -25 speeds, timing reference levels of
1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZWE is less than tLZWE for any given device. These parameters are guaranteed by
design and not 100% tested.
8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05047 Rev. **
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