CY7C1061DV33 Datasheet, PDF (4/10 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Static RAM

PRELIMINARY
CY7C1061DV33
AC Switching Characteristics Over the Operating Range ^[5]
–10
Parameter
Description
Min.
Max.
Unit
Read Cycle
t_power
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
Write Cycle^{[9, 10]}
V_CC(typical) to the first access^[6]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE₁ LOW/CE₂ HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z^[7]
CE₁ LOW/CE₂ HIGH to Low-Z^[7]
CE₁ HIGH/CE₂ LOW to High-Z^[7]
CE₁ LOW/CE₂ HIGH to Power-Up^[8]
CE₁ HIGH/CE₂ LOW to Power-Down^[8]
Byte Enable to Data Valid
Byte Enable to Low-Z
Byte Disable to High-Z
100
µs
10
ns
10
ns
3
ns
10
ns
5
ns
1
ns
5
ns
3
ns
5
ns
0
ns
10
ns
5
ns
1
ns
5
ns
t_WC
Write Cycle Time
10
ns
t_SCE
CE₁ LOW/CE₂ HIGH to Write End
7
ns
t_AW
Address Set-up to Write End
7
ns
t_HA
Address Hold from Write End
0
ns
t_SA
Address Set-up to Write Start
0
ns
t_PWE
WE Pulse Width
7
ns
t_SD
Data Set-up to Write End
5.5
ns
t_HD
t_LZWE
t_HZWE
Data Hold from Write End
WE HIGH to Low-Z^[7]
WE LOW to High-Z^[7]
0
ns
3
ns
5
ns
t_BW
Byte Enable to End of Write
7
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use
output loading shown in part a) of the AC test loads, unless specified otherwise.
6. t_POWER gives the minimum amount of time that the power supply should be at typical V_CC values until the first memory access can be performed.
7. t_HZOE, t_HZCE, t_HZWE, t_HZBE and t_LZOE, t_LZCE, t_\LZWE, t_LZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state
voltage.
8. These parameters are guaranteed by design and are not tested.
9. The internal Write time of the memory is defined by the overlap of CE₁ LOW (CE₂ HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
Document #: 38-05476 Rev. *C
Page 4 of 10
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