CY7B9950 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer

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CY7B9950
Absolute Maximum Conditions
Parameter
Description
V_DD
V_DD
V_IN(MIN)
V_IN(MAX)
T_S
T_A
T_J
Ø_JC
Ø_JA
ESD_HBM
UL-94
Operating Voltage
Operating Voltage
Input Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
MSL
Moisture Sensitivity Level
F_IT
Failure in Time
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to V_SS
Relative to V_DD
Non-functional
Functional
Functional
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
MIL-STD-883, Method 3015
@1/8 in.
Manufacturing Testing
Min.
Max.
2.375
2.625
2.97
3.63
V_SS – 0.3
–
–65
–
V_DD + 0.3
+150
–40
+85
–
155
–
42
–
105
2000
–
V–0
1
10
Unit
V
V
V
V
°C
°C
°C
°C/W
°C/W
V
ppm
DC Electrical Specifications @ 2.5V
Parameter
Description
Conditions
Min.
Max. Unit
V_DD
V_IL
V_IH
V_IHH[9]
V_IMM[9]
V_ILL[9]
I_IL
I₃
I_PU
I_PD
V_OL
V_OH
I_DDQ
2.5 Operating Voltage
2.5V ± 5%
2.375
2.625
V
Input LOW Voltage
REF, FB and sOE# Inputs
–
0.7
V
Input HIGH Voltage
1.7
–
V
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
3-Level Inputs
V_DD – 0.4
–
V
(TEST, FS, nF[1:0], PE/HD) (These pins are normally
wired to V_DD,GND or unconnected.)
V_DD/2 – 0.2
–
V_DD/2 + 0.2
0.4
V
V
Input Leakage Current
3-Level Input DC Current
Input Pull-up Current
Input Pull-down Current
Output LOW Voltage
Output HIGH Voltage
Quiescent Supply Current
V_IN = V_DD/G_ND,V_DD = max. (REF and FB inputs)
HIGH, V_IN = V_DD
MID, V_IN = V_DD/2
LOW, V_IN = V_SS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV, PE/HD)
V_IN = V_SS, V_DD = max.
V_IN = V_DD, V_DD = max., (sOE#)
I_OL = 12 mA (PE/HD = L/H), (nQ[0:1])
I_OL = 20 mA (PE/HD = MID),(nQ[0:1])
I_OH = –12 mA (PE/HD = L/H),(nQ[0:1])
I_OH = –20 mA (PE/HD = MID),(nQ[0:1])
V_DD = max., TEST = MID, REF = LOW, sOE# = LOW,
outputs not loaded
–5
–
–50
–200
–25
–
–
–
2.0
2.0
–
5
µA
200
µA
50
µA
–
µA
–
µA
100
µA
0.4
V
0.4
V
–
V
–
V
2
mA
I_DD
Dynamic Supply Current @ 100 MHz
150
mA
C_IN
Input Pin Capacitance
4
pF
Note:
9. These inputs are normally wired to V_DD, GND or unconnected. Internal termination resistors bias unconnected inputs to V_DD/2.
Document #: 38-07338 Rev. *B
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