CY62148 Datasheet, PDF (4/7 Pages) Cypress Semiconductor – 512K x 8 Static RAM

PRELIMINARY
Switching Waveforms
Read Cycle No.1^[10,11]
ADDRESS
DATA OUT
t_RC
t_AA
t_OHA
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)^[11,12]
ADDRESS
t_RC
CE
CY62148
DATA VALID
62148-5
t_ACE
OE
DATA OUT
V_CC
SUPPLY
CURRENT
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
Write Cycle No. 1 (CE Controlled)^[13,14]
ADDRESS
CE
t_SA
DATA VALID
t_HZOE
t_HZCE
HIGH
IMPEDANCE
t_PD
50%
ICC
ISB
62148-6
t_WC
t_SCE
WE
DATA I/O
t_AW
t_PWE
t_SD
DATA VALID
Notes:
10. Device is continuously selected. OE, CE = V_IL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = V_IH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
t_HA
t_HD
62148-7
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