CY62136ESL_11 Datasheet, PDF (4/15 Pages) Cypress Semiconductor – 2 Mbit (128K x 16) Static RAM

CY62136ESL MoBL^
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground potential .................–0.5 V to 6.0 V
DC voltage applied to outputs
in High-Z State^{[4, 5]}...........................................–0.5 V to 6.0 V
DC input voltage^{[4, 5]} ........................................–0.5 V to 6.0 V
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage............................................ >2001 V
(MIL-STD-883, Method 3015)Latch up current ....... >200 mA
Operating Range
Device
CY62136ESL
Range
Industrial
Ambient
Temperature
V_CC^[6]
–40 °C to +8 5°C 2.2 V–3.6 V,
and 4.5 V–5.5 V
Electrical Characteristics
Over the Operating Range
Parameter
V_OH
V_OL
V_IH
V_IL
I_IX
I_OZ
I_CC
I_SB1^[8]
I_SB2^[8]
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input leakage current
Output leakage current
V_CC Operating supply
current
Automatic CE
power-down current —
CMOS inputs
Automatic CE
power-down current —
CMOS inputs
Test Conditions
2.2 < V_CC < 2.7
I_OH = –0.1 mA
2.7 < V_CC < 3.6
I_OH = –1.0 mA
4.5 < V_CC < 5.5
I_OH = –1.0 mA
2.2 < V_CC < 2.7
I_OL = 0.1 mA
2.7 < V_CC < 3.6
I_OL = 2.1 mA
4.5 < V_CC < 5.5
I_OL = 2.1 mA
2.2 < V_CC < 2.7
2.7 < V_CC < 3.6
4.5 < V_CC < 5.5
2.2 < V_CC < 2.7
2.7 < V_CC < 3.6
4.5 < V_CC < 5.5
GND < V_I < V_CC
GND < V_O < V_CC, Output disabled
f = f_max = 1/t_RC
f = 1 MHz
V_CC = V_CCmax
I_OUT = 0 mA, CMOS levels
CE > V_CC 0.2 V, V_IN > V_CC – 0.2 V or V_IN < 0.2 V,
f = f_max (Address and data only),
f = 0 (OE, BHE, BLE and WE), V_CC = V_CC(max)
CE >
f = 0,
V_CC
V_CC
–
=
V0._C²_C^V_(m^, _a^V_xI)N
>
V_CC
–
0.2
V
or
V_IN
<
0.2
V,
Min
2.0
2.4
2.4
–
–
–
1.8
2.2
2.2
–0.3
–0.3
–0.5
–1
–1
–
–
–
–
45 ns
Typ ^[7]
Max
–
–
–
–
–
–
–
0.4
–
0.4
–
0.4
–
V_CC + 0.3
–
V_CC + 0.3
–
V_CC + 0.5
–
0.6
–
0.8
–
0.8
–
+1
–
+1
15
20
2
2.5
1
7
1
7
Unit
V
V
V
V
A
A
mA
A
A
Notes
4. V_IL(min) = –2.0 V for pulse durations less than 20 ns.
5. V_IH(max) = V_CC + 0.75 V for pulse durations less than 20 ns
6. Full Device AC operation assumes a 100 s ramp time from 0 to V_CC (min) and 200 s wait time after V_CC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V_CC = 3 V, and V_CC = 5V, T_A = 25 °C.
8. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I_SB1 / I_SB2 / I_CCDR spec. Other inputs can be left floating.
Document #: 001-48147 Rev. *C
Page 4 of 15
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