CY62126BV Datasheet, PDF (4/9 Pages) Cypress Semiconductor – 64K x 16 Static RAM

CY62126BV
Switching Characteristics^[5] Over the Operating Range
62126BV–55
62126BV–70
Parameter
Description
Min. Max. Min. Max. Unit
READ CYCLE
t_RC
Read Cycle Time
t_AA
Address to Data Valid
t_OHA
Data Hold from Address Change
t_ACE
CE LOW to Data Valid
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[7]
OE HIGH to High Z^{[6, 7]}
CE LOW to Low Z^[7]
CE HIGH to High Z^{[6, 7]}
t_PU
CE LOW to Power-Up
t_PD
CE HIGH to Power-Down
t_DBE
Byte Enable to Data Valid
t_LZBE
Byte Enable to LOW Z^[7]
t_HZBE
Byte Disable to HIGH Z^[6,7]
WRITE CYCLE^[8]
55
70
ns
55
70
ns
10
10
ns
55
70
ns
25
35
ns
5
5
ns
20
25
ns
10
10
ns
20
25
ns
0
0
ns
55
70
ns
25
35
ns
5
5
ns
20
25
ns
t_WC
Write Cycle Time
55
70
ns
t_SCE
CE LOW to Write End
45
60
ns
t_AW
Address Set-Up to Write End
45
60
ns
t_HA
Address Hold from Write End
0
0
ns
t_SA
Address Set-Up to Write Start
0
0
ns
t_PWE
WE Pulse Width
40
50
ns
t_SD
Data Set-Up to Write End
25
30
ns
t_HD
t_LZWE
t_HZWE
Data Hold from Write End
WE HIGH to Low Z^[7]
WE LOW to High Z^[6,7]
0
0
ns
5
5
ns
25
25
ns
t_BW
Byte Enable to End of Write
45
60
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 30-pF load capacitance.
6. t_HZOE, t_HZCE, t_HZWE, and t_HZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, t_HZWE is less than t_LZWE, and t_HZBE is less than t_LZBE, for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for
further conditions from BHE and BLE.
4