CY2SSTU877_06 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer

PRELIMINARY
CY2SSTU877
AC Timing Specifications
Parameter
F_CLK[1,2]
T_DC
T_ODC
T_LOCK
T_OENB
T_ODIS
Description
Clock Frequency (Max)
Clock Frequency (Application)
Input Duty Cycle
Output Duty Cycle
PLL Lock Time
Output Enable Time
Output Disable Time
Tjitt (cc)
Tjit (Period)
Tjit (H-Period)
Cycle-to-cycle jitter
Period jitter
Half Period Cycle-to-cycle jitter
T_(φ)
T_(φ)DYN
T_SKEW
S_LR(O)
S_LR(I)
Static Phase Offset
Dynamic Phase Offset
Clock Skew
Output Slew Rate
Input Slew Rate
Conditions
Room temp and nominal V_DDQ
Room temp and nominal V_DDQ
OE to any CLKT/ CLKC[0:9]
OE to any CLKT/ CLKC[0:9]
Min.
125
250
40
48
–
–
–
–40
–30
Above 270 MHz
–45
Below 270 MHz
–60
Average 1000 cycles
–50
–40
–
CLKT/ CLKC[0:9], FB_OUTT,
1.5
FB_OUTC
CLK_INT, CLK_INC, FB_INT,
1
FB_INC
OE
0.5
Max.
500
500
60
52
15
8
8
40
30
45
60
50
40
40
4
4
Unit
MHz
MHz
%
%
µs
ns
ns
ps
ps
ps
ps
ps
ps
ps
V/ns
V/ns
V/ns
Figure 1. Test Loads for Timing Measurement
Notes:
1. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for
low speed system debug).
2. Application clock frequency indicates a range over which the PLL must meet all timing requirements.
Document #: 38-07575 Rev. *E
Page 4 of 9