CY26121_08 Datasheet, PDF (4/7 Pages) Cypress Semiconductor – PacketClock™ Spread Spectrum Clock Generator

CY26121
AC Electrical Specifications ^[3]
Parameter
Description
DC Output Duty Cycle
ER Rising Edge Rate
EF
Falling Edge Rate
tj
RMS Clock Cycle-to-Cycle
Jitter
Condition
Min
Duty Cycle is defined in Figure 2, 50% of V_DD
45
Output Clock Edge Rate, Measured from 20% to 0.8
80% of V_DD, C_LOAD = 15 pF See Figure 3.
Output Clock Edge Rate, Measured from 80% to 0.8
20% of V_DD, C_LOAD = 15 pF See Figure 3.
RMS cycle-to-cycle jitter with Spread on.
Measured at V_DD/2.
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
Clock
Output
t₁
t₂
V_DD
50% of V_DD
0V
Typ.
50
1.4
Max Unit
55
%
V/ns
1.4
V/ns
15
40
ps
Figure 3. ER = (0.6 x V_DD) /t3, EF = (0.6 x V_DD) /t4
t
3
t
4
V
DD
80% of V
DD
Clock
Output
20% of V
DD
0V
Note
3. Guaranteed by Characterization, not 100% tested.
Document #: 38-07350 Rev. *A
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