CY23FS08-04 Datasheet, PDF (4/11 Pages) Cypress Semiconductor – FailSafe™ 1.8V Zero Delay Buffer

CY23FS08-04
Table 3. FailSafe Timing Table
Parameter
Description
Conditions
Min
Max
Unit
t_FSL
Fail#/Safe Assert Delay
Measured at 80% to 20%, Load = 15 pF
See Figure 3
ns
t_FSH Fail#/Safe Deassert Delay Measured at 80% to 20%, Load = 15 pF See Figure 3
ns
DCXO and capture range
Failsafe has DCXO for tracking to incoming reference clock. The CY23FS08-04 is configured its capture range of approx +/- 100ppm
with using pullable crystal that specified in Table 7.
Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range
Reference
Reference + 100 ppm
Reference - 100 ppm
Reference Off
Output
Fail#/Safe
t_FSL
Output + 100 ppm
Output - 100 ppm
t_FSH
Time
Document Number: 001-17042 Rev. **
Page 4 of 11
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