CY22313 Datasheet, PDF (4/9 Pages) Cypress Semiconductor – Two-PLL Clock Generator with Direct Rambus-TM (Lite) Support

CY22313
Switching Characteristics^[3]
Parameter
Description
F_PPM
Frequency Error
Conditions
Part to Part, does not include PCB variation^[8]
Over commercial temperature range^[9]
DC
t_{3_54, 2.5}
t_{3_54, 1.675}
t_{4_54, 2.5}
t_{4_54, 1.675}
t_CR, t_CF
t_CR-CF
t₅
Output Duty Cycle
Duty cycle for all outputs, measured at V_DD/2
54MOUT Rising Edge Slew Rate 20% to 80% of V_DD54, V_DD54 = 2.5V
54MOUT Rising Edge Slew Rate 20% to 80% of V_DD54, V_DD54 = 1.675V
54MOUT Falling Edge Slew Rate 80% to 20% of V_DD54, V_DD54 = 2.5V
54MOUT Falling Edge Slew Rate 80% to 20% of V_DD54, V_DD54 = 1.675V
CLK/CLKB Rise and Fall Times 20% to 80% of output voltage
CLK/CLKB Rise and Fall
Difference^[10]
Lock Time^[11]
20% to 80% of output voltage
PLL lock time from power-up
Phase Noise Specifications
Min.
45
0.75
0.35
0.75
0.35
160
Typ.
±5
±2
50
1.2
0.5
1.2
0.5
Max.
±10
±5
55
4.0
2.5
4.0
2.5
400
100
Unit
PPM
PPM
%
V/ns
V/ns
V/ns
V/ns
ps
ps
1.0 3.0 ms
Parameter
Description
Phase Noise
Phase Noise
Conditions
54 MHz at 10-kHz offset
53.946 MHz at 10-kHz offset
Min. Typ. Max. Unit
–95
dBc
–92
dBc
Jitter Specifications^[3]
Parameter
Description
t_{6_LCLK}
t_{6_54, 2.5}
LCLK Jitter^[12]
54MOUT Jitter^[12]
t_{6_54, 1.675}
t_{7_LCLK}
t_{7_54}
LCLK 1000 Cycle Jitter^[13]
54MOUT 1000 Cycle Jitter^[13]
t₈
CLK/CLKB 1–6 Cycle Jitter^[14]
t₉
CLK/CLKB Long-term Jitter^[15]
t₁₀
CLK/CLKB Duty Cycle Error^[16]
Conditions
Cycle-Cycle Jitter – 9.216 MHz
Cycle-Cycle Jitter – 54 MHz, V_DD = 2.5V
Cycle-Cycle Jitter – 53.946 MHz, V_DD = 2.5V
Cycle-Cycle Jitter – 54 MHz, V_DD = 1.675V
Cycle-Cycle Jitter – 53.946 MHz, V_DD = 1.675V
1000 Cycle Jitter – 9.216 MHz
1000 Cycle Jitter – 54 MHz,
1000 Cycle Jitter – 53.946 MHz,
Cycle-Cycle Jitter, 1–6 Cycles, 400 MHz
Cycle-Cycle Jitter, 1–6 Cycles, 300 MHz
Long-term Jitter, 400 MHz
Long-term Jitter, 300 MHz
Cycle-Cycle Duty Cycle Error, 400 MHz
Cycle-Cycle Duty Cycle Error, 300 MHz
Notes:
8. Tested across three lots on same board, PCB boards can vary more than ± 5 PPM.
9. Crystal should not be heated for this test, only IC.
10. Measured on same pin of a single device.
11. Lock Time shown in Figure 2.
12. LCLK and 54MOUT Cycle-Cycle Jitter shown in Figure 3.
13. LCLK and 54MOUT 1000 Cycle Jitter shown in Figure 4.
14. CLK/CLKB 1-6 Cycle Jitter specification is absolute value of worst case deviation, and is shown in Figure 5 and Figure 6.
15. CLK/CLKB Long Term Jitter shown in Figure 7.
16. CLK/CLKB Duty Cycle Error shown in Figure 8.
Typ. Max. Unit
250 ps
150 ps
150 ps
250 ps
250 ps
250 ps
400 ps
400 ps
50 ps
70 ps
300 ps
400 ps
50 ps
70 ps
Document #: 38-07434 Rev. *E
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