C9851 Datasheet, PDF (4/14 Pages) Cypress Semiconductor – Clock Generator for Pentium III Server and Workstation Applications

PRELIMINARY
C9851
Clock Generator for Pentium^III Server and Workstation Applications
AC Parameters (VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V ±5%, TA = 0°C to +70°C)
133 MHz Host 100 MHz Host
Symbol
Parameter
Min
Max
Min
Max Units
TPeriod
CPU[(1:6), (1:6)#] period -
7.35
7.65
9.85
10.2
nS
Tr / Tf
TSKEW1
CPU[(1:6), (1:6)#] rise and fall times
skew from any CPU pair to any CPU pair
175
450
175
450
pS
-
150
-
150
pS
TSKEW2
skew from package to package
-
100
-
100
pS
TCCJ
CPU[(1:6), (1:6)#] Cycle to Cycle Jitter
-
150
-
150
pS
Vover
Vunder
Vcrossover
CPU[(1:6), (1:6)#] Overshoot
CPU[(1:6), (1:6)#] Undershoot
CPU(1:6) to CPU(1:6)# crossover point
Voh+0.2
Voh+0.2
V
-0.2
-0.2
V
45%Voh 55%Voh 45%Voh 55%Voh
V
Tduty
Duty Cycle
45
55
45
55
%
Notes
1, 2
2, 3
2, 4, 5
2, 4, 5
2, 4, 5
2,10
2, 10
2, 4
2, 4
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
Tduty
3V(MREF, MREF_B) period
3V(MREF, MREF_B) high time
3V(MREF, MREF_B) low time
3V(MREF, MREF_B) rise and fall times
3VMREF to 3VMREF_B skew
3V(MREF, MREF_B) Cycle to Cycle Jitter
Duty Cycle
15.0
15.3
20.0
20.4
nS
4, 5
5.25
-
7.5
-
nS
2, 6
5.05
-
7.3
-
nS
2, 7
0.4
1.6
0.4
1.6
nS
2, 3
-
250
-
250
pS
2, 4, 5, 11
-
250
-
250
pS
2, 4, 5
45
55
45
55
%
2, 4
TPeriod
THIGH
TLOW
Tr / Tf
TCCJ
Tduty
3V66 period
3V66 high time
3V66 low time
3V66 rise and fall times
3V66 Cycle to Cycle Jitter
Duty Cycle
15.0
16.0
15.0
15.2
nS
5.25
-
5.25
-
nS
5.05
-
5.05
-
nS
0.5
2.0
0.5
2.0
nS
-
300
-
300
pS
45
55
45
55
%
1, 2, 4
2,6
2, 7
2, 3
2, 4, 5
2, 4
TPeriod
Tr / Tf
TCCJ
Tduty
REF period
REF rise and fall times
REFCycle to Cycle Jitter
Duty Cycle
69.8413
71.0
69.8413
71.0
nS
1.0
4.0
1.0
4.0
nS
-
1000
-
1000
pS
45
55
45
55
%
1, 2, 4
2, 3
2, 4
2, 4
tpZL, tpZH
tpLZ, tpZH
tstable
Output enable delay (all outputs)
Output disable delay (all outputs)
All clock Stabilization from power-up
1.0
10.0
1.0
10.0
nS
9
1.0
10.0
1.0
10.0
nS
9
3
3
mS
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) continued
Note 1: This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1uS duration, with a crystal
center frequency of 14.31818MHz
Note 2: All outputs loaded as per table 2 below.
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for
CPU[(1:6), (1:6)#] signals. (see Figs.7A & 7B)
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figs.7A
& 7B).
Note 5: This measurement is applicable with Spread ON or Spread OFF.
Note 6: Probes are placed on the pins, and measurements are acquired at 2.4V (see Figs. 7A & 7B)
Note 7: Probes are placed on the pins, and measurements are acquired at 0.4V. (see Figs. 7A & 7B)
Note 9: As this function is available through SEL(A,B), therefore, the time specified is guaranteed by design.
Note 10: Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.
Note 11: 3VMref and 3VMref_b are 180 degrees out of phase, therefore, the skew is measured between the rising edge of one and the falling edge
of the other.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: [phone], Fax: [phone]
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
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