CY8C24123A_06 Datasheet, PDF (39/55 Pages) Cypress Semiconductor – PSoC® Mixed-Signal Array

CY8C24x23A Final Data Sheet
3. Electrical Specifications
Table 3-30. 2.7V AC Digital Block Specifications
Function
All
Functions
Timer
Description
Maximum Block Clocking Frequency
Capture Pulse Width
Counter
Maximum Frequency, With or Without Capture
Enable Pulse Width
Dead Band
Maximum Frequency, No Enable Input
Maximum Frequency, Enable Input
Kill Pulse Width:
Asynchronous Restart Mode
Synchronous Restart Mode
Disable Mode⁰
Maximum Frequency
CRCPRS Maximum Input Clock Frequency
(PRS Mode)
CRCPRS Maximum Input Clock Frequency
(CRC Mode)
SPIM
Maximum Input Clock Frequency
SPIS
Transmitter
Maximum Input Clock Frequency
Width of SS_ Negated Between Transmissions
Maximum Input Clock Frequency
Receiver Maximum Input Clock Frequency
Min
Typ
Max
Units
12.7
MHz
100^a
–⁰
–
–
100^a
–⁰
–
–
–
–
–⁰
ns
12.7
MHz
–⁰
ns
12.7
MHz
12.7
MHz
20
–
100^a
–⁰
100^a
–⁰
–
–
–
–
–
–
–
–
–
–
100^a
–⁰
–
–
–
–
–
ns
–⁰
ns
–⁰
ns
12.7
MHz
12.7
MHz
12.7
MHz
6.35
MHz
4.23
ns
–⁰
ns
12.7
MHz
12.7
MHz
a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
Notes
2.4V < Vdd < 3.0V.
Maximum data rate at 3.17 MHz due to 2 x over
clocking.
Maximum data rate at 1.59 MHz due to 8 x over
clocking.
Maximum data rate at 1.59 MHz due to 8 x over
clocking.
October 17, 2006
Document No. 38-12028 Rev. *F
39
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