CYP15G0201DXB_05 Datasheet, PDF (36/46 Pages) Cypress Semiconductor – Dual-channel HOTLink II™ Transceiver

CYP15G0201DXB
CYV15G0201DXB
CYW15G0201DXB
Table 21. Package Coordinate Signal Allocation
Ball
ID Signal Name Signal Type
Ball
ID Signal Name
Signal Type
A1
VCC POWER
C5
RXLE
LVTTL IN PU
A2
INA2+ CML IN
C6
RXRATE LVTTL IN PD
A3 OUTA2– CML OUT
C7
GND
GROUND
A4
VCC POWER
C8
GND
GROUND
A5
INA1+ CML IN
C9
SPDSEL 3-LEVEL SEL
A6 OUTA1– CML OUT
C10
PARCTL 3-LEVEL SEL
A7
VCC POWER
C11 RFMODE 3-LEVEL SEL
A8
VCC POWER
C12
VCC
POWER
A9
INB2+ CML IN
C13 SDASEL 3-LEVEL SEL
A10 OUTB2– CML OUT
C14
BOE[2] LVTTL IN PU
A11
VCC POWER
D1
VCC
POWER
A12
INB1+ CML IN
D2
VCC
POWER
A13 OUTB1– CML OUT
D3
NC
Not Connected
A14
VCC POWER
D4
TXRATE LVTTL IN PD
B1
TDO
LVTTL 3-S OUT D5 RXMODE[1] 3-LEVEL SEL
B2
INA2– CML IN
D6 RXMODE[0] 3-LEVEL SEL
B3 OUTA2+ CML OUT
D7
GND
GROUND
B4
VCC POWER
D8
GND
GROUND
B5
INA1– CML IN
D9
TCLK
LVTTL IN PD
B6 OUTA1+ CML OUT
D10
TDI
LVTTL IN PU
B7
NC
Not Connected D11
INSELB LVTTL IN
B8
NC
Not Connected D12
INSELA LVTLL IN
B9
INB2– CML IN
D13
VCC
POWER
B10 OUTB2+ CML OUT
D14
VCC
POWER
B11
VCC POWER
E1
BISTLE LVTTL IN PU
B12
INB1– CML IN
E2 FRAMCHAR 3-LEVEL SEL
B13 OUTB1+ CML OUT
E3 TXMODE[1] 3-LEVEL SEL
B14 BOE[3] LVTTL IN PU
E4 TXMODE[0] 3-LEVEL SEL
C1
NC
Not Connected
E5
BOE[0] LVTTL IN PU
C2
RFEN LVTTL IN PD
E6
BOE[1] LVTTL IN PU
C3
VCC POWER
E7
GND
GROUND
C4
LPEN LVTTL IN PD
E8
GND
GROUND
G13
NC
Not Connected
K4
RXDA[6] LVTTL OUT
G14
VCC POWER
K5
TXDA[4] LVTTL OUT
H1
VCC POWER
K6
TXCLKA LVTTL IN PD
H2
NC
Not Connected
K7
GND
GROUND
H3
GND GROUND
K8
GND
GROUND
H4
GND GROUND
K9
NC
Not Connected
H5
GND GROUND
K10
RXOPB LVTTL 3-S OUT
H6
GND GROUND
K11 RXCLKB+ LVTTL I/O PD
H7
GND GROUND
K12 RXCLKB– LVTTL I/O PD
H8
GND GROUND
K13
LFIB
LVTTL OUT
H9
GND GROUND
K14
TXCLKB LVTTL IN PD
Ball
ID Signal Name Signal Type
E9
TXOPB LVTTL IN PU
E10 TXPERB LVTTL OUT
E11 TXCKSEL 3-LEVEL SEL
E12 RXCKSEL 3-LEVEL SEL
E13 TRSTZ LVTTL IN PU
E14
TMS LVTTL IN PU
F1 DECMODE 3-LEVEL SEL
F2
OELE LVTTL IN PU
F3 RXCLKC+ LVTTL 3-S OUT
F4 RXSTA[2] LVTTL OUT
F5 RXSTA[1] LVTTL OUT
F6
GND GROUND
F7
GND GROUND
F8
GND GROUND
F9
GND GROUND
F10 TXDB[4] LVTTL IN
F11 TXDB[3] LVTTL IN
F12 TXDB[2] LVTTL IN
F13 TXDB[1] LVTTL IN
F14 TXDB[0] LVTTL IN
G1
VCC POWER
G2
NC
Not Connected
G3
GND GROUND
G4
GND GROUND
G5
GND GROUND
G6
GND GROUND
G7
GND GROUND
G8
GND GROUND
G9
GND GROUND
G10
GND GROUND
G11
GND GROUND
G12
GND GROUND
M9 TXRSTn LVTTL IN PU
M10
NC
Not Connected
M11 RXSTB[0] LVTTL OUT
M12
VCC POWER
M13 RXDB[5] LVTTL OUT
M14 RXDB[6] LVTTL OUT
N1 RXCLKA+ LVTTL I/O PD
N2 TXCTA[0] LVTTL IN
N3 TXDA[6] LVTTL IN
N4
VCC POWER
N5 TXDA[1] LVTTL IN
Document #: 38-02058 Rev. *H
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