 English |
|
|
|
|
|
|
|
| CY8CPLC20 Datasheet, PDF (36/44 Pages) Cypress Semiconductor – Powerline Communication Solution | |||
| |||
| ◁ |
CY8CPLC20
10. Packaging Information
This chapter illustrates the packaging specifications for the CY8CPLC20 PLC device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Note Emulation tools may require a larger area on the target PCB than the chipâs footprint. For a detailed description of the emulation
toolsâ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
10.1 Packaging Dimensions
Figure 10-1. 28-Pin (210-Mil) SSOP
51-85079 *C
Document Number: 001-48325 Rev. *E
Page 36 of 44
[+] Feedback
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese