CY8C29466_11 Datasheet, PDF (36/61 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip Low power at high speed

CY8C29466, CY8C29566
CY8C29666, CY8C29866
Table 27. AC Chip-Level Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
Notes
F_MAX
Maximum frequency of signal on row input or
–
row output.
–
12.3
MHz
SR_{POWER_UP} Power supply slew rate
–
–
250
V/ms V_DD slew rate during
power-up
T_POWERUP
Time from end of POR to CPU executing code
–
tjit_IMO^[19] 24 MHz IMO cycle-to-cycle jitter (RMS)
–
16
100
200
700
ms Power-up from 0 V. See the
System Resets section of
the PSoC Technical
Reference Manual
ps N = 32
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
–
300
900
tjit_PLL ^[19]
24 MHz IMO period jitter (RMS)
24 MHz IMO cycle-to-cycle jitter (RMS)
–
100
400
–
200
800
ps N = 32
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
–
300
1200
24 MHz IMO period jitter (RMS)
–
100
700
PLL
Enable
F_PLL
Figure 12. PLL Lock Timing Diagram
T_PLLSLEW
24 MHz
PLL
Gain ⁰
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
T_PLLSLEWLOW
24 MHz
F_PLL
PLL
Gain ¹
Figure 14. External Crystal Oscillator Startup Timing Diagram
32K
Select
T_OS
32 kHz
F_32K2
Note
19. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 38-12013 Rev. *S
Page 36 of 61
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