CY7C1381D_13 Datasheet, PDF (32/37 Pages) Cypress Semiconductor – 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM

CY7C1381D
CY7C1383D
CY7C1383F
1. ZZ Pin Issue
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■ TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■ SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■ WORKAROUND
Tie the ZZ pin externally to ground.
■ FIX STATUS
Fix was done for the 72Mb RAM9 Synchronous SRAMs and 72M RAM9 NoBL SRAMs devices. Fixed devices have a new
revision. The following table lists the devices affected and the new revision after the fix.
2. JTAG Functionality
■ PROBLEM DEFINITION
The problem occurs only when the device is operated in the JTAG test mode.During this mode, the JTAG circuitry can perform
incorrectly by delivering the incorrect data or the incorrect scan chain length.
■ TRIGGER CONDITIONS
Several conditions can trigger this failure mode.
1. The device can deliver an incorrect length scan chain when operating in JTAG mode.
2. Some Byte Write inputs only recognize a logic HIGH level when in JTAG mode.
3. Incorrect JTAG data can be read from the device when the ZZ input is tied HIGH during JTAG operation.
■ SCOPE OF IMPACT
The device fails for JTAG test. This does not impact the normal functionality of the device.
■ WORKAROUND
1.Perform JTAG testing with these devices in “BYPASS mode”.
2.Do not use JTAG test.
Document Number: 38-05544 Rev. *P
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