CY8C32_11 Datasheet, PDF (31/119 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family
Data Sheet
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
„ Active
„ Alternate Active
„ Sleep
„ Hibernate
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 illustrates the allowable transitions between
power modes.
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source Active Clocks
Regulator
Active
Primary mode of operation, all Wakeup, reset, Any interrupt
peripherals available (program- manual register
mable)
entry
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Alternate
Active
Similar to Active mode, and is Manual register
typically configured to have
entry
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
Manual register Comparator, ILO/kHzECO
entry
PICU, I²C, RTC,
CTW, LVD
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Hibernate
All subsystems automatically Manual register
disabled
entry
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
PICU
Only hibernate regulator
active.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Active
Alternate
Active
Sleep
Wakeup
Time
–
–
<15 µs
Hibernate <100 µs
Current
(typ)
1.2 mA^[12]
–
1 µA
200 nA
Code
Execution
Yes
User
defined
No
No
Digital
Resources
All
All
I²C
None
Analog Clock Sources
Resources Available
All
All
All
All
Comparator ILO/kHzECO
None
None
Wakeup Sources
–
–
Comparator,
PICU, I²C, RTC,
CTW, LVD
PICU
Reset
Sources
All
All
XRES, LVD,
WDR
XRES
Note
12. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 63.
Document Number: 001-56955 Rev. *J
Page 31 of 119
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