CY8C24123A_09 Datasheet, PDF (31/55 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

CY8C24123A
CY8C24223A, CY8C24423A
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 31. 5V and 3.3V AC Chip-Level Specifications
Symbol
F_IMO24
Description
Internal Main Oscillator Frequency for
24 MHz
F_IMO6
Internal Main Oscillator Frequency for
6 MHz
F_CPU1
F_CPU2
F_48M
F_24M
F_32K1
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
Digital PSoC Block Frequency
Internal Low Speed Oscillator
Frequency
Min
23.4
5.75
0.93
0.93
0
0
15
Typ
Max Units
Notes
24 24.6^[10,11,12] MHz Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
12 on page 17. SLIMO mode = 0.
6 6.35^[10,11,12] MHz Trimmed for 5V or 3.3V operation
using factory trim values. See Figure
12 on page 17. SLIMO mode = 1.
24
24.6^[10,11] MHz
12
12.3^[11,12] MHz
48 49.2^[10,11,13] MHz Refer to the AC Digital Block
Specifications.
24
24.6^[11,13] MHz
32
64
kHz
F_32K2
External Crystal Oscillator
– 32.768
–
kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
F_PLL
PLL Frequency
– 23.986
–
MHz Is a multiple (x732) of crystal
frequency.
Jitter24M2 24 MHz Period Jitter (PLL)
–
–
600
ps
T_PLLSLEW PLL Lock Time
0.5
T_PLLSLEWSL PLL Lock Time for Low Gain Setting
0.5
OW
T_OS
External Crystal Oscillator Startup to 1% –
T_OSACC
External Crystal Oscillator Startup to
–
100 ppm
–
–
1700
2800
Jitter32k 32 kHz Period Jitter
–
100
10
50
2620
3800
ms
ms
ms
ms The crystal oscillator frequency is
within 100 ppm of its final value by
the end of the T_osacc period. Correct
operation assumes a properly
loaded 1 uW maximum drive level
32.768 kHz crystal. 3.0V ≤ Vdd ≤
5.5V, -40 ^oC ≤ T_A ≤ 85 ^oC.
ns
T_XRST
DC24M
External Reset Pulse Width
24 MHz Duty Cycle
10
–
40
50
–
μs
60
%
Step24M
Fout48M
24 MHz Trim Step Size
48 MHz Output Frequency
–
46.8
50
48.0
–
kHz
49.2^[10,12] MHz Trimmed. Using factory trim values.
Jitter24M1P 24 MHz Period Jitter (IMO)
–
300
ps
Peak-to-Peak
Jitter24M1R 24 MHz Period Jitter (IMO) Root Mean –
–
Squared
600
ps
F_MAX
Maximum frequency of signal on row
–
–
input or row output.
12.3
MHz
T_RAMP
Supply Ramp Time
0
–
–
μs
Notes
10. 4.75V < Vdd < 5.25V.
11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
12. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
13. See the individual user module data sheets for information on maximum frequencies for user modules.
Document Number: 38-12028 Rev. *J
Page 31 of 55
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