CY8C20X36_09 Datasheet, PDF (31/39 Pages) Cypress Semiconductor – CapSense Applications

CY8C20X36/46/66/96
Packaging Information
This section illustrates the packaging specifications for the CY8C20x36/46/66/96 PSoC device, along with the thermal impedances
for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 15. 16-pin QFN No E-pad 3x3mm Package Outline (Sawn)
Figure 16. 24-Pin (4x4 x 0.6 mm) QFN
001-09116 *D
Document Number: 001-12696 Rev. *F
001-13937 *B
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