CY8C20111 Datasheet, PDF (30/34 Pages) Cypress Semiconductor – CapSense Express-One Button and Two Button Capacitive Controllers

PRELIMINARY
CY8C20111, CY8C20121
11.5 AC Electrical Specifications
11.5.1 5V and 3.3V AC General Purpose I/O Specifications
Parameter
Description
Min
TRise
Rise time, strong mode,
15
Cload = 50 pF
TFall
Fall time, strong mode,
10
Cload = 50 pF
Max
Unit
Notes
80
ns V_DD = 3.10V to 3.6V and 4.75V to
5.25V, 10% - 90%
50
ns V_DD = 3.10V to 3.6V and 4.75V to
5.25V, 10% - 90%
11.5.2 2.7V AC General Purpose I/O Specifications
Parameter
Description
TRise
TFall
Rise time, strong mode,
Cload = 50 pF
Fall time, strong mode,
Cload = 50 pF
Min
Max
Unit
Notes
15
100
ns V_DD = 2.4V to 2.90V, 10% - 90%
10
70
ns V_DD = 2.4V to 2.90V, 10% - 90%
11.5.3 AC I²C Specifications
Parameter
Description
F_SCLI²C SCL clock frequency
Standard
Mode
Min Max
0 100
T_HDSTAI²C Hold time (repeated) START condition. After 4.0 –
this period, the first clock pulse is generated
T_LOWI²C LOW period of the SCL clock
4.7 –
T_HIGHI²C HIGH period of the SCL clock
4.0 –
T_SUSTAI²C Setup time for a repeated START condition 4.7 –
T_HDDATI²C Data hold time
0–
T_SUDATI²C Data setup time
250 –
T_SUSTOI²C Setup time for STOP condition
4.0 –
T_BUFI²C BUS free time between a STOP and START 4.7 –
condition
T_SPI²C
Pulse width of spikes suppressed by the
input filter
––
Fast Mode
Min Max
0 400
0.6 –
1.3 –
0.6 –
0.6 –
0
–
100 –
0.6 –
1.3 –
0 50
Units
Notes
kbps Fast mode not supported for
V_DD < 3.0V
µs
µs
µs
µs
µs
ns
µs
µs
ns
Figure 12. Definition of Timing for Fast/Standard Mode on the I²C Bus
SDA
t_f
t_LOWI2C
t_r
t_SUDATI2C
t_f
t_HDSTAI2C
SCL
S
t_HDSTAI2C
t_HDDATI2C
t_HIGHI2C
t_SUSTAI2C
Sr
t_SPI2C
t_r
t_BUFI2C
t_SUSTOI2C
P
S
Document Number: 001-53516 Rev. **
Page 30 of 34
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