W530-02 Datasheet, PDF (3/8 Pages) Cypress Semiconductor – Frequency-multiplying, Peak-reducing EMI Solution

W530-02
The W530-02 also allows for frequency multiplication in order
to determine the relationship between the input and output
frequencies. Simply compare the min. frequency of the input
and output ranges selected (use 12.5 instead of 13 for this
calculation, though). The multiplication options are: 0.25,
0.5,1.0, 2.0, and 4.0.
Functional Description
The W530-02 uses a PLL to frequency modulate an input
clock. The result is an output clock whose frequency is slowly
swept over a narrow band near the input signal. The basic
circuit topology is shown in Figure 1. The input reference
signal is divided by Q and fed to the phase detector. A signal
from the VCO is divided by P and fed back to the phase
detector also. The PLL will force the frequency of the VCO
output signal to change until the divided output signal and the
divided reference signal match at the phase detector input.
The output frequency is then equal to the ratio of P/Q times the
reference frequency. The unique feature of the Spread
Spectrum Frequency Timing Generator is that a modulating
waveform is superimposed at the input to the VCO. This
Clock Input
Reference Input
Freq.
Divider
Q
V_DD
Phase
Detector
Charge
Pump
causes the VCO output to be slowly swept across a predeter-
mined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum
process has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI
reduction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (IR1:2, OR1:2 pins), the frequency
range can be set (see Table 1 and Table 3). Spreading
percentage is set with pins MW0:2, as shown in Table 2.
A larger spreading percentage improves EMI reduction.
However, large spread percentages may either exceed
system maximum frequency ratings or lower the average
frequency to a point where performance is affected. For these
reasons, spreading percentages between 0.5% and 2.5% are
most common.
CLKOUT
Σ
VCO
Post
Dividers
(EMI suppressed)
Feedback
Divider
P
Modulating
Waveform
PLL
GND
Figure 1. Conceptual Block Diagram
Spread Spectrum Frequency Timing Generation
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
Contrast the typical clock EMI with the Cypress Spread
Spectrum Frequency Timing Generation EMI. Notice the spike
in the typical clock. This spike can make systems fail
quasi-peak EMI testing. The FCC and other regulatory
agencies test for peak emissions. With spread spectrum
enabled, the peak energy is much lower (at least 8 dB)
because the energy is spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI
reduction. The modulation scheme used to accomplish the
maximum reduction in EMI is shown in Figure 3. The period of
the modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the
spreading frequency band as a percent of the programmed
average output frequency, symmetric about the programmed
average frequency. This method is always shown using the
expression f_Center ± X_MOD% in the frequency spread selection
table.
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this
frequency. The output signal is swept from the lower edge of
the band to the maximum frequency. The expression for this
approach is f_MAX – X_MOD%. Whenever this expression is used,
Cypress has taken care to ensure that f_MAX will never be
exceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
Document #: 38-07190 Rev. *A
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