W164_02 Datasheet, PDF (3/12 Pages) Cypress Semiconductor – Spread Spectrum Desktop/Notebook System Frequency Generator

W164
Power-on
Reset
Timer
V_DD
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
10 kΩ
(Load Option 1)
10 kΩ
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
W164
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Hold
Output
Low
QD
Data
Latch
Jumper Options
10 kΩ
V_DD
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Resistor Value R
W164
Figure 2. Input Logic Selection Through Jumper Option
Serial Data Interface
The W164 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W164 initializes
with default register settings. Therefore, the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management func-
tions. Table 2 summarizes the control functions of the serial
data interface.
Operation
Data is written to the W164 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
100- and 66.6-MHz selections that are provided by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, inter- Production PCB testing.
nal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Document #: 38-07169 Rev. *A
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