SM561 Datasheet, PDF (3/8 Pages) Cypress Semiconductor – Spread Spectrum Clock Generator

SM561
Table 1. Frequency and Spread% Selection (Center Spread)
54-108 M Hz (Low Range)
In p u t
Frequency
(M Hz)
54 - 60
60 - 70
70 - 80
80 - 100
100 - 108
S1=M
S0=M
(% )
3.6
3.5
3.3
3.0
2.6
S1=M
S0=0
(% )
3.1
3.0
2.8
2.5
2.3
S1=1
S0=0
(% )
2.6
2.5
2.4
2.1
1.9
S1=0
S0=0
(% )
2.1
2.0
1.9
1.7
1.5
S1=0
S0=M
(% )
1.8
1.7
1.6
1.4
1.3
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
in d ic a te d .
108 - 166 M H z (H igh R ange)
In p u t
Frequency
(M Hz)
180 - 120
120 -130
130 - 140
140 - 150
150 - 166
S1=1
S0=M
(% )
2.3
2.3
2.3
2.2
2.1
S1=0
S0=1
(% )
1.7
1.7
1.7
1.6
1.5
S1=1
S0=1
(% )
1.1
1.1
1.1
1.1
1.0
S1=M
S0=1
(% )
0.9
0.9
0.9
0.9
0.8
Select the
Frequency and
Center Spread %
desired and then
set S1, S0 as
in d ic a te d .
Tri-level Logic
With binary logic, four states can be programmed with two
control lines where as Tri-level Logic can program nine logic
states using two control lines. Tri-level Logic in the SM561 is
implemented by defining a third logic state in addition to the
standard logic “1” and “0”. Pins 6 and 7 of the SM561
recognize a logic state by the voltage applied to the respective
pin. These states are defined as “0” (Low), “M” (Middle), and
VDD = 3.3 VDC
“1” (One). Each of these states have a defined voltage range
that is interpreted by the SM561 as a “0”, “M,” or “1” logic state.
Refer to Table 1 for voltage ranges for each logic state. By
using two equal value resistors (typically 20K) the “M” state
can be easily programmed. Pins 6 or 7 can be tied directly to
ground or V_DD for Logic “0” or “1,” respectively.
VDD = 3.3 VDC
VDD = 3.3 VDC
SM561
SM561
SM561
20K
7 1.65 VDC
7
7
6 0 VDC
20K
6
6
5
5
5
EX. 1
EX. 2
Figure 1.
EX. 3
Document #: 38-07021 Rev. *C
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