S6E1A1 Datasheet, PDF (3/3 Pages) Cypress Semiconductor – 32-bit Microcontroller FM0+ Family

FactSheet
5. BLOCK DIAGRAM
S6E1A11/S6E1A12
To PIN-Function-Ctrl
SWCLK,
SWDIO
INITX
X0
X1
X0A
X1A
CROUT
AVCC,
AVSS
AVRH
(only 48/52pin
PKG)
ANxx
ADTG
TIOAx
TIOBx
AINx
BINx
ZINx
IC0x
FRCKx
DTTI0X
RTO0x
SW-DP
Cortex-M0+ Core
@40MHz(Max)
NVIC
Bit Band
Wrapper
System ROM
table
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
WatchDog Timer
(Hardware)
CSV
CLK
Main
Osc
Sub
Osc
PLL
CR
4MHz
Source Clock
CR
100kHz
12-bit A/D Converter
Unit 0
Base Timer
16-bit 4ch./
32-bit 2ch.
QPRC
1ch.
A/D Activation
Compare 6ch.
16-bit Input Capture
4ch.
16-bit Free-run Timer
3ch.
16-bit Output
Compare 6ch.
Waveform Generator
3ch.
Fast
GPIO
MTB
Flash I/F
Security
LVD Ctrl
IRQ-Monitor
Watch Counter
Real-Time Clock
External Interrupt
Controller
8pin + NMI
MODE-Ctrl
Low-speed CR
Prescaler
Peripheral Clock Gating
GPIO
IGTRGx
16-bit PPG
3ch.
Multi-function Timer
Multi-function Serial I/F
3ch.
(with FIFO)
On-Chip SRAM
6 Kbyte
On-Chip Flash
56 Kbyte/
88 Kbyte
DMAC
2ch.
Power-On
Reset
LVD
Regulator
C
RTCCO,
SUBOUT
INTx
NMIX
MD0
To Fast GPIO
PIN-Function-Ctrl
P0x,
P1x,
.
.
.
Pxx
SCKx
SINx
SOTx
SCSx
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S6E1A1_NP710-00001-1v0-E, July 16, 2014