CY7C1329G Datasheet, PDF (3/16 Pages) Cypress Semiconductor – 2-Mb (64K x 32) Pipelined Sync SRAM

CY7C1329G
Pin Definitions
Name
TQFP
I/O
Description
A₀, A₁, A
37,36,
32,33,34,
35,44,45,
46,47,48,
49,81,82,
99,100
Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled
at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂,
and CE₃ are sampled active. A₁^{, A}₀ feed the 2-bit counter.
BW_A, BW_B,
BW_C, BW_D
GW
93,94,95,
96
88
BWE
87
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte
Synchronous Writes to the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising
edge of CLK, a global Write is conducted (ALL bytes are written, regardless of
the values on BW_[A:D] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a Byte Write.
CLK
89
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst
operation.
CE₁
98
CE₂
97
CE₃
92
OE
86
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with ^CE₂ and _CE3 to select/deselect the device. _{ADSP is ignored}
if CE₁ is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with _CE1 and _CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE₁ and CE₂ to select/deselect the device. Not connected
for BGA. Where referenced, CE₃ is assumed active throughout this document
for BGA.
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of
the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during
the first clock of a Read cycle when emerging from a deselected state.
ADV
83
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW.
Synchronous When asserted, it automatically increments the address in a burst cycle.
ADSP
84
ADSC
85
ZZ
64
Input-
Synchronous
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, A is captured in the address registers. A₁, A₀ are
also loaded into the burst counter. When _ADSP and _ADSC are both asserted,
only _ADSP is recognized. _ASDP is ignored when _CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, A is captured in the address registers. A₁, A₀ are
also loaded into the burst counter. When _ADSP and _ADSC are both asserted,
only _ADSP is recognized.
Input-
ZZ “sleep” Input, active HIGH. This input, when HIGH places the device in a
Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQ_A, DQ_B
DQ_C, DQ_D
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
2,3,6,7,8,9,
12,3,18,19,
22,23,24,25,
28,29
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by “A” during the previous clock rise
of the Read cycle. The direction of the pins is controlled by _OE. When _OE is
asserted LOW, the pins behave as outputs. When HIGH, DQ are placed in a
three-state condition.
Document #: 38-05393 Rev. *A
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