CY7C1046BV33 Datasheet, PDF (3/8 Pages) Cypress Semiconductor – 1M x 4 Static RAM

PRELIMINARY
CY7C1046BV33
AC Test Loads and Waveforms
3.3V
R1 317Ω
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
3.3V
R1 317 Ω
3.3V
OUTPUT
R2
351Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2 GND
351Ω
Rise Time: 1 V/ns
1046BV33–3
ALL INPUT PULSES
90%
10%
90%
10%
Fall Time: 1 V/ns
1046BV33–4
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167Ω
1.73V
Switching Characteristics^[4] Over the Operating Range
7C1046BV33-10 7C1046BV33-12 7C1046BV33-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t_RC
Read Cycle Time
t_AA
Address to Data Valid
t_OHA
Data Hold from Address Change
t_ACE
CE LOW to Data Valid
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Data Valid
OE LOW to Low Z^[6]
OE HIGH to High Z^{[5, 6]}
CE LOW to Low Z^[6]
CE HIGH to High Z^{[5, 6]}
t_PU
CE LOW to Power-Up
t_PD
CE HIGH to Power-Down
WRITE CYCLE^{[7, 8]}
10
12
15
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
4
6
7
ns
0
0
0
ns
5
6
7
ns
3
3
3
ns
5
6
7
ns
0
0
0
ns
10
12
15
ns
t_WC
Write Cycle Time
t_SCE
CE LOW to Write End
t_AW
Address Set-Up to Write End
t_HA
Address Hold from Write End
t_SA
Address Set-Up to Write Start
t_PWE
WE Pulse Width
t_SD
Data Set-Up to Write End
t_HD
t_LZWE
t_HZWE
Data Hold from Write End
WE HIGH to Low Z^[6]
WE LOW to High Z^{[5, 6]}
Shaded areas contain advance information.
10
12
15
ns
7
10
12
ns
7
10
12
ns
0
0
0
ns
0
0
0
ns
7
10
12
ns
5
7
8
ns
0
0
0
ns
3
3
3
ns
5
6
7
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I_OL/I_OH and 30-pF load capacitance.
5. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
Document #: 38-05170 Rev. **
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