CY7B991_11 Datasheet, PDF (3/21 Pages) Cypress Semiconductor – Programmable Skew Clock Buffer

Pinouts
Figure 1. Pin Configuration – 32-Pin PLCC/LCC Package
3F1
4F0
4F1
V_CCQ
V_CCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
CY7B991
CY7B992
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
V_CCN
1Q0
1Q1
GND
GND
CY7B991
CY7B992
Table 1. Pin Definition
Signal Name
IO
REF
I
FB
FS
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
V_CCN
V_CCQ
GND
I
I
I
I
I
I
I
O
O
O
O
PWR
PWR
PWR
Description
Reference frequency input. This input supplies the frequency and timing against which all functional
variations are measured.
PLL feedback input (typically connected to one of the eight outputs).
Three level frequency range select. See Table 2.
Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 3.
Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 3.
Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 3.
Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 3.
Three level select. See “Test Mode” on page 5 under the “Block Diagram Description” on page 4.
Output pair 1. See Table 3.
Output pair 2. See Table 3.
Output pair 3. See Table 3.
Output pair 4. See Table 3.
Power supply for output drivers.
Power supply for internal circuitry.
Ground.
Document Number: 38-07138 Rev. *I
Page 3 of 21
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