CY62137FV30_09 Datasheet, PDF (3/12 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137FV30 MoBL^®
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ...........................................................-0.3V to 3.9V
DC Voltage Applied to Outputs
in High Z state ^{[4, 5]} ............................................-0.3V to 3.9V
DC Input Voltage ^{[4, 5]} .......................................–0.3V to 3.9V
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage ......................................... > 2001V
(MIL–STD–883, Method 3015)
Latch up Current .................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
V_CC ^[6]
CY62137FV30LL Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V
Auto-E –40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Min Typ^[1] Max Min Typ^[1] Max ^Unit
V_OH
Output HIGH Voltage 2.2 < V_CC < 2.7
I_OH = –0.1 mA
2.0
2.0
V
2.7 < V_CC < 3.6
I_OH = –1.0 mA
2.4
2.4
V
V_OL
Output LOW Voltage 2.2 < V_CC < 2.7
I_OL = 0.1 mA
0.4
0.4 V
2.7 < V_CC < 3.6
I_OL = 2.1mA
0.4
0.4 V
V_IH
Input HIGH Voltage 2.2 < V_CC < 2.7
1.8
V_CC + 0.3 1.8
V_CC + 0.3 V
2.7 < V_CC < 3.6
2.2
V_CC + 0.3 2.2
V_CC + 0.3 V
V_IL
Input LOW Voltage
2.2 < V_CC < 2.7
–0.3
0.6 –0.3
0.6 V
2.7 < V_CC < 3.6
–0.3
0.8 –0.3
0.8 V
I_IX
Input Leakage Current GND < V_I < V_CC
–1
+1 –4
+4 μA
I_OZ
Output Leakage
GND < V_O < V_CC, Output disabled
–1
Current
+1 –4
+4 μA
I_CC
V_CC Operating Supply f = f_max = 1/t_RC
V_CC = V_CC(max)
Current
f = 1 MHz
I_OUT = 0 mA
CMOS levels
13
18
1.6 2.5
15
25 mA
2
3
I_SB1
I_SB2 ^[7]
Automatic CE Power CE > V_CC – 0.2V,
Down Current – CMOS V_IN > V_CC – 0.2V, V_IN < 0.2V
Inputs
f = f_max (address and data only),
f = 0 (OE, WE, BHE, and BLE), V_CC = 3.60V
Automatic CE Power CE > V_CC – 0.2V,
Down Current – CMOS _{VIN > VCC – 0.2V or VIN < 0.2V,}
Inputs
f = 0, V_CC = 3.60V
1
5
1
5
1
20 μA
1
20 μA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
C_IN
C_OUT
Input Capacitance
Output Capacitance
Test Conditions
T_A = 25°C, f = 1 MHz,
V_CC = V_CC(typ)
Max
Unit
10
pF
10
pF
Notes
4. V_IL(min) = –2.0V for pulse durations less than 20 ns.
5. V_IH(max)=V_CC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V_CC(min) and 200 μs wait time after V_CC stabilization.
7. Only chip enable (CE) and byte enables (BHE and BLE) are tied to CMOS levels to meet the I_SB2 / I_CCDR specification. Other inputs can be left floating.
Document Number: 001-07141 Rev. *F
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