CY2XF33 Datasheet, PDF (3/7 Pages) Cypress Semiconductor – High Performance LVDS Oscillator with Frequency Margining - Pin Control

PRELIMINARY
CY2XF33
Absolute Maximum Conditions
Parameter
Description
V_DD
V_IN[1]
T_S
T_J
ESD_HBM
Θ_JA[2]
Supply Voltage
Input Voltage, DC
Temperature, Storage
Temperature, Junction
ESD Protection (Human Body Model)
Thermal Resistance, Junction to Ambient
Condition
Relative to V_SS
Non operating
JEDEC STD 22-A114-B
0 m/s airflow
Min
–0.5
–0.5
–55
–40
2000
Max
4.4
V_DD+0.5
135
135
–
64
Unit
V
V
°C
°C
V
°C/W
Operating Conditions
Parameter
Description
Min
Typ Max
Unit
V_DD
3.3V Supply Voltage Range
2.5V Supply Voltage Range
3.135 3.3 3.465
V
2.375 2.5 2.625
V
T_PU
Power Up Time for V_DD to Reach Minimum Specified Voltage (Power Ramp 0.05
–
500
ms
is Monotonic)
T_A
Ambient Temperature (Commercial)
Ambient Temperature (Industrial)
0
–
70
°C
–40
–
85
°C
DC Electrical Characteristics
Parameter
Description
I_DD[3]
Operating Supply Current
Condition
Min
Typ
Max
Unit
V_DD = 3.465V, CLK = 150 MHz, output
–
terminated
–
120
mA
V_DD = 2.625V, CLK = 150 MHz, output
–
terminated
–
115
mA
V_OD
LVDS Differential Output Voltage V_DD = 3.3V or 2.5V, defined in Figure 3 247
–
454
mV
as terminated in Figure 2
ΔV_OD
Change in V_OD between Comple- V_DD = 3.3V or 2.5V, defined in Figure 3
–
–
50
mV
mentary Output States
as terminated in Figure 2
V_OS
LVDS Offset Output Voltage
V_DD = 3.3V or 2.5V, defined in Figure 4 1.125
–
1.375
V
as terminated in Figure 2
ΔV_OS
Change in V_OS between Comple- V_DD = 3.3V or 2.5V, R_TERM = 100Ω
mentary Output States
between CLK and CLK#
–
–
50
mV
V_IH
V_IL
I_IH0
I_IH1
I_IL0
I_IL1
C_IN0[4]
C_IN1[4]
Input High Voltage
Input Low Voltage
Input High Current, FS0 pin
Input High Current, FS1 pin
Input Low Current, FS0 pin
Input Low Current, FS1 pin
Input Capacitance, FS0 pin
Input Capacitance, FS1 pin
Input = V_DD
Input = V_DD
Input = V_SS
Input = V_SS
0.7*V_DD –
–
V
–
–
0.3*V_DD
V
–
–
115
μA
–
–
10
μA
–50
–
–
μA
–20
–
–
μA
–
15
–
pF
–
4
–
pF
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. I_DD includes ~4 mA of current that is dissipated externally in the output termination resistors.
4. Not 100% tested, guaranteed by design and characterization.
Document Number: 001-53148 Rev. *B
Page 3 of 7
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