CY29949_08 Datasheet, PDF (3/7 Pages) Cypress Semiconductor – 2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer

CY29949
Maximum Ratings^[2]
Maximum Input Voltage Relative to V_SS:............. V_SS – 0.3V
Maximum Input Voltage Relative to V_DD:............. V_DD + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum ESD Protection .............................................. 2 kV
Maximum Power Supply:................................................ 5.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions must be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V_in and V_out should be constrained to the range:
V_SS < (V_in or V_out) < V_DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V_SS or V_DD).
Maximum Input Current: ............................................ ±20 mA
DC Parameters (V_DD = V_DDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range)
Parameter
Description
Conditions
Min
Typ
Max
Unit
V_IL
V_IH
I_IL
I_IH
V_PP
V_CMR
V_OL
V_OH
I_DDQ
I_DD
Input Low Voltage
Input High Voltage
Input Low Current^[3]
Input High Current^[3]
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range^[4]
PECL_CLK
Output Low Voltage^[5]
Output High Voltage^[5]
Quiescent Supply Current
Dynamic Supply Current
V_DD = 3.3V, PECL_CLK single ended
V_DD = 2.5V, PECL_CLK single ended
All other inputs
V_DD = 3.3V, PECL_CLK single ended
V_DD = 2.5V, PECL_CLK single ended
All other inputs
V_DD = 3.3V
V_DD = 2.5V
I_OL = 20 mA
I_OH = –20 mA, V_DD = 3.3V
I_OH = –20 mA, V_DD = 2.5V
V_DD = 3.3V, Outputs at 100 MHz,
CL = 30 pF
1.49
–
1.825
V
1.10
–
1.45
V_SS
–
0.8
2.135
–
2.42
V
1.75
–
2.0
2.0
–
V_DD
–
–
–100
µA
–
–
100
300
–
1000
mV
V_DD – 2.0 – V_DD – 0.6 V
V_DD – 1.2 – V_DD – 0.6
–
–
0.4
V
2.5
–
–
V
1.8
–
–
5
7
mA
–
200
–
mA
V_DD = 3.3V, Outputs at 160 MHz,
CL = 30 pF
–
330
–
V_DD = 2.5V, Outputs at 100 MHz,
CL = 30 pF
–
140
–
V_DD = 2.5V, Outputs at 160 MHz,
CL = 30 pF
–
235
–
Zout
C_in
Output Impedance
Input Capacitance
V_DD = 3.3V
V_DD = 2.5V
12
15
18
Ω
14
18
22
–
4
–
pF
Notes
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The V_CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V_CMR
range and the input lies within the V_PP specification.
5. Driving series or parallel terminated 50Ω (or 50Ω to V_DD/2) transmission lines.
Document #: 38-07289 Rev. *E
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