CY241V08A-02 Datasheet, PDF (3/6 Pages) Cypress Semiconductor – MPEG Clock Generator with VCXO

PRELIMINARY
CY241V08A-02
Absolute Maximum Conditions
Supply Voltage (V_DD) ........................................–0.5 to +7.0V
DC Input Voltage...................................... –0.5V to V_DD + 0.5
Storage Temperature (Non-condensing)..... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Pullable Crystal Specifications^[1]
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883................. > 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Parameter
Description
F_NOM
Nominal crystal frequency
C_LNOM
R₁
R₃/R₁
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
DL
Crystal drive level
F_3SEPHI
F_3SEPLO
C₀
C₀/C₁
C₁
Third overtone separation from 3*F_NOM
Third overtone separation from 3*F_NOM
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
Recommended Operating Conditions
Comments
Parallel resonance, fundamental mode, AT
cut
Fundamental mode
Ratio used because typical R₁ values are
much less than the maximum spec
No external series resistor assumed
High side
Low side
Min.
–
–
–
3
150
300
–
–
180
14.4
Typ.
27
14
–
–
–
–
–
–
–
18
Max.
–
–
25
–
–
–
–150
7
250
21.6
Unit
MHz
pF
Ω
–
µW
ppm
ppm
pF
–
fF
V_DD
T_A
C_LOAD
t_PU
Parameter
Description
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all V_DD pins to reach minimum specified
voltage (power ramps must be monotonic)
Min.
3.135
0
–
0.05
Typ.
3.3
–
–
–
Max. Unit
3.465 V
70
°C
15
pF
500 ms
DC Electrical Specifications
Parameter
I_OH
I_OL
C_IN
V_VCXO
f_∆XO[2]
Name
Output HIGH Current
Output LOW Current
Input Capacitance
VCXO Input Range
VCXO Pullability Range
I_VDD
Supply Current
Description
V_OH = V_DD – 0.5V, V_DD = 3.3V
V_OL = 0.5V, V_DD = 3.3V
Except XIN, XOUT pins
Low Side
High Side
Min.
12
12
–
0
–
115
–
Typ. Max. Unit
24
–
mA
24
–
mA
–
7
pF
–
V_DD
V
–
–115 ppm
–
–
ppm
–
35
mA
AC Electrical Specifications (V_DD = 3.3V) ^[3]
Parameter^[3]
Name
Description
Min. Typ. Max. Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 1, 50% of V_DD 45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% 0.8 1.4
to 80% of V_DD, C_LOAD = 15 pF. See Figure 2.
– V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80% 0.8 1.4
to 20% of V_DD, C_LOAD = 15 pF. See Figure 2.
– V/ns
t₉
Peak-to-peak Period Jitter
27-MHz Clock Jitter
–
– 100 ps
Notes:
1. Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M
2. –115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
3. Not 100% tested.
Document #: 38-07674 Rev. *A
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