CY14MB064J_13 Datasheet, PDF (3/30 Pages) Cypress Semiconductor – 64-Kbit (8 K x 8) Serial (I2C) nvSRAM

CY14MB064J
CY14ME064J
Pinouts
Figure 1. 8-pin SOIC pinout
A0 1
8
A1 2 _CY14MX064J1 7
A2
3
Top View
not to scale
6
V_SS 4
5
V_CC
WP
SCL
SDA
V_CAP
A1
A2
V_SS
1
8
2 _CY14MX064J2 7
3
Top View
not to scale
6
4
5
V_CC
WP
SCL
SDA
Figure 2. 16-pin SOIC pinout
NC 1
16 VCC
NC 2
15 NC
NC _{3 CY14MX064J3} 14 V_CAP
NC ₄ ^{Top View} 13 A2
not to scale
WP 5
12 SDA
A0 ₆
11 ^SCL
NC ₇
VSS ₈
10 A1
9 HSB
Pin Definitions
Pin Name I/O Type
Description
SCL
SDA
Input
Clock. Runs at speeds up to a maximum of f_SCL.
Input/Output I/O. Input/Output of data through I²C interface.
Output: Is open-drain and requires an external pull-up resistor.
WP
A2–A0 ^[3]
Input
Input
Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be
left open if not connected.
Slave Address. Defines the slave address for I²C. This pin is internally pulled LOW and hence can be
left open if not connected.
HSB
Input/Output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t_HHHD) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
V_CAP
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It
must never be connected to ground.
NC
No connect No Connect. This pin is not connected to the die.
V_SS Power supply Ground
V_CC Power supply Power supply
Note
3. A0 pin is not available in CY14MX064J2.
Document Number: 001-65051 Rev. *H
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