CY14B256KA_12 Datasheet, PDF (3/27 Pages) Cypress Semiconductor – 256-Kbit (32 K × 8) nvSRAM with Real Time Clock

CY14B256KA
Pinouts
Pin Definitions
Figure 1. 48-pin SSOP pinout
V_CAP
NC^[1]
1
2
A_{14 3}
A_{12 4}
A_{7 5}
A_{6 6}
A_{5 7}
INT ₈
A_{4 9}
48 V_CC
47 _NC^[1]
46 _HSB
45 _WE
44
A₁₃
43 A₈
42 A₉
41 NC
48 - SSOP 40 A₁₁
NC 10
(x8)
39 NC
NC 11 _{Top View}
38 NC
NC
V_SS
12
13
(not to scale)
37
36
NC
V_SS
NC ₁₄
35 ^NC
V_RTCbat
15
34
V_RTCcap
DQ0 16
33 DQ6
A_{3 17}
32 OE
A_{2 18}
31 A₁₀
A_{1 19}
30 CE
A_{0 20}
29 DQ7
DQ1 ₂₁
DQ2 ₂₂
Xout 23
28 DQ5
27 DQ4
26 DQ3
Xin 24
25 V_CC
Pin Name
A₀–A₁₄
DQ₀–DQ₇
NC
WE
CE
OE
X_out[2]
X_in[2]
V_RTCcap[2]
V_RTCbat[2]
[2]
INT
V_SS
V_CC
HSB
V_CAP
I/O Type
Description
Input Address inputs. Used to select One of the 32,768 bytes of the nvSRAM.
Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation.
No connect No connect. This pin is not connected to the die.
Input
Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
Deasserting OE HIGH causes the I/O pins to tristate.
Output Crystal connection. Drives crystal on start up.
Input Crystal connection. For 32.768 kHz crystal.
Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if V_RTCbat is used.
Power supply Battery supplied backup RTC supply voltage. Left unconnected if V_RTCcap is used.
Output Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
Ground Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the Device. 3.0 V +20%, –10%
Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress.
When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (t_HHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Notes
1. Address expansion for 1-Mbit. NC pin not connected to die.
2. Left unconnected if RTC feature is not used.
Document Number: 001-55720 Rev. *G
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